DS2227 Maxim, DS2227 Datasheet - Page 2

• Manufacturer Part Number: DS2227
• Description: The DS2227 combines voltage monitoring circuitry with lithium-backed memory in a flexible architecture that can be accessed as 128k x 32, 256k x 16, or 512k x 8 bits
• Manufacturer: Maxim

select pins for each of the four banks of onboard memories (see Figure 1). For operation as a 512k x 8 NV
SRAM Stik, tie all data lines from each bank together (i.e., all D0s together, all D1s together, etc.). Read
enables and write enables are also tied together. For operation as a 256k x 16 NV SRAM Stik, tie the data
lines from two banks together. Chip enables, read enables, and write enables from these banks are also
tied together. Connection to the DS2227 is made by using an industry-standard, 72-position SIMM socket
DS9072-72V (AMP part number 821824-8). These SIMM sockets are also available in perpendicular,
inclined, or parallel mount, depending on the height available. See the DS907x SipStik
available from Dallas Semiconductor.
READ MODE
The DS2227 executes a read cycle whenever
and
defines which byte of data is to be accessed. Valid data will be available to the eight data I/O pins within
t
also satisfied. If
occurring signal (
address access.
WRITE MODE
The DS2227 is in the write mode whenever both
address inputs are stable. The latter occurring falling edge of
write cycle. The write cycle is terminated by the earlier rising edge of
be kept valid throughout the write cycle.
(t
write cycles to avoid bus contention. However, if the output bus has been enabled (
then
DATA RETENTION MODE
The DS2227 provides fully functional capability for V
protection for V
support circuitry. The DS2227 constantly monitors V
SRAM automatically write-protects itself, all inputs become “don’t care” and all outputs become high
impedance. As V
energy source to RAM to retain data. During power-up, when V
the power switching circuit connects the external V
Normal RAM operation can resume after V
The DS2227 checks lithium status to warn of potential data loss. Each time that V
the DS2227, the battery voltage is checked with a precision comparator. If the battery supply is less than
2.0 volts, the second memory access to the device is inhibited.
determined by a three-step process. First, a read cycle is performed to any location in memory, in order to
save the contents of that location. A subsequent write cycle can then be executed to the same memory
location, altering data. If the next read cycle fails to verify the written data, then the battery voltage is less
than 2.0V and data is in danger of being corrupted.
The DS2227 also provides battery redundancy. In many applications data integrity is paramount. The
DS2227 provides two batteries for each SRAM and an internal isolation switch to select between them.
During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the
other automatically takes over. The switch between batteries is transparent to the user.
ACC
WR
) before another cycle can be initiated. The
OE
(access time) after the last address input signal is stable, providing that
WE
(Output Enable) are active (low). The unique address specified by the 17 address inputs (A
will disable the outputs to t
CC
CC
OE
CE
less than 4.25 volts. Data is maintained in the absence of V
falls below approximately 3.0 volts, a power switching circuit connects a lithium
and
or
OE
CE
) and the limiting parameter is either t
times are not satisfied, then data access must be measured from the later
ODW
from its falling edge.
WE
CC
exceeds 4.5 volts.
WE
must return to the high state for a minimum recovery time
2 of 10
OE
(Write Enable) is inactive (high) and
WE
CC
control signal should be kept inactive (high) during
to RAM and disconnects the lithium energy source.
and
CC
CC
. Should the supply voltage decay, the NV
CE
greater than 4.5 volts and guarantees write
CE
signals are in the active (low) state after
CC
or
CO
rises above approximately 3.0 volts,
CE
WE
Battery status can, therefore, be
for
or
will determine the start of the
CE
CE
WE
or t
CC
. All address inputs must
and
CC
without any additional
OE
OE
power is restored to
CE
for
CE
access times are
and
OE
TM
(Chip Enable)
rather than
connectors
OE
0
DS2227
active)
- A
16
)