STR911FAW46 STMicroelectronics, STR911FAW46 Datasheet - Page 25

• Manufacturer Part Number: STR911FAW46
• Description: ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR911FAW46

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

STR91xFAxxx
3.12.2
3.13
Note:
3.13.1
Battery supply
An optional stand-by voltage from a battery or other source may be connected to pin VBATT
to retain the contents of SRAM in the event of a loss of the main digital supplies (V
V
VBATT pin when the voltage of V
battery supply, the LVD must be enabled.
The VBATT pin also supplies power to the RTC unit, allowing the RTC to function even when
the main digital supplies (V
it is possible to select whether or not to power from VBATT only the RTC unit, or power the
RTC unit and the SRAM when the STR91xFA device is powered off.
System supervisor
The STR91xFA monitors several system and environmental inputs and will generate a
global reset, a system reset, or an interrupt based on the nature of the input and
configurable settings. A global reset clears all functions on the STR91xFA, a system reset
will clear all but the Clock Control Unit (CCU) settings and the system status register. At any
time, firmware may reset individual on-chip peripherals. System supervisor inputs include:
●
●
●
●
●
●
GR: means the input causes Global Reset, SR: means the input causes System Reset
The CPU may read a status register after a reset event to determine if the reset was caused
by a watchdog timer timeout or a voltage supply drop out. This status register is cleared only
by a power up reset.
Supply voltage brownout
Each operating voltage source (V
Detect (LVD) circuitry. The LVD will generate an early warning interrupt to the CPU when
voltage sags on either V
applications because the system can perform an orderly shutdown before the batteries
become too weak. The voltage trip point to cause a brown out interrupt is typically 0.25V
above the LVD dropout thresholds that cause a reset.
CPU firmware may prevent all brown-out interrupts by writing to interrupt mask registers at
run-time.
DDQ)
GR: CPU voltage supply (V
GR: I/O voltage supply (V
GR: Power-Up condition
SR: Watchdog timer timeout
SR: External reset pin (RESET_INn)
SR: JTAG debug reset command
. The SRAM will automatically switch its supply from the internal V
DD
DD
or V
Doc ID 13495 Rev 6
and V
DDQ
DDQ
DD
DD
DD
) drop out or brown out
) drop out or brown out
voltage inputs. This is an advantage for battery powered
drops below the LVD threshold. In order to use the
DDQ
and V
) are switched off. By configuring the RTC register,
DDQ
) is monitored separately by the Low Voltage
Functional overview
DD
source to the
DD
25/102
and