5M570ZM100I5N Altera Corporation, 5M570ZM100I5N Datasheet - Page 10
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5M570ZM100I5N
Manufacturer Part Number
5M570ZM100I5N
Description
IC MAX V CPLD 570 LE 100-MBGA
Manufacturer
Altera Corporation
Series
MAX® Vr
Datasheet
1.5M240ZT100C5N.pdf
(30 pages)
Specifications of 5M570ZM100I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
9.0ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of Gates
-
Number Of I /o
74
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
100-TFBGA
Lead Free Status
Vendor undefined
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M570ZM100I5N
Manufacturer:
ALTERA
Quantity:
630
3–10
Power Consumption
Timing Model and Specifications
Figure 3–2. Timing Model for MAX V Devices
MAX V Device Handbook
I/O Pin
INPUT
I/O Input Delay
f
f
t
IN
You can use the Altera
Analyzer to estimate the device power.
For more information about these power analysis tools, refer to the
Power Estimator for Altera CPLDs User Guide
in volume 3 of the Quartus II Handbook.
MAX V devices timing can be analyzed with the Altera Quartus
of industry-standard EDA simulators and timing analyzers, or with the timing model
shown in
MAX V devices have predictable internal delays that allow you to determine the
worst-case timing of any design. The software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for device-wide
performance evaluation.
You can derive the timing characteristics of any signal path from the timing model
and parameters of a particular device. You can calculate external timing parameters,
which represent pin-to-pin timing delays, as the sum of the internal parameters.
For more information, refer to
Input Routing
Global Input Delay
Memory
Delay
Flash
User
t
DL
t
GLOB
Figure
Data-In/LUT Chain
3–2.
To Adjacent LE
Register Control
®
LUT Delay
t
Logic Element
Delay
PowerPlay Early Power Estimator and PowerPlay Power
LUT
t
C
t
R4
AN629: Understanding Timing in Altera
t
COMB
t
t
t
t
PRE
CLR
CO
SU
t
H
Register Delays
Chapter 3: DC and Switching Characteristics for MAX V Devices
t
C4
and the
Data-Out
Combinational Path Delay
From Adjacent LE
PowerPlay Power Analysis
Output Routing
t
Delay
FASTIO
t
IODR
t
IOE
Output and Output Enable
®
May 2011 Altera Corporation
II software, a variety
Data Delay
Output
Delay
t
PowerPlay Early
t
t
OD
XZ
ZX
CPLDs.
Power Consumption
chapter
I/O Pin