5M160ZE64I5N Altera Corporation, 5M160ZE64I5N Datasheet - Page 21
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5M160ZE64I5N
Manufacturer Part Number
5M160ZE64I5N
Description
IC MAX V CPLD 160 LE 64-EQFP
Manufacturer
Altera Corporation
Series
MAX® Vr
Datasheet
1.5M240ZT100C5N.pdf
(30 pages)
Specifications of 5M160ZE64I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
160
Number Of Macrocells
128
Number Of Gates
-
Number Of I /o
54
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
64-TQFP Exposed Pad
Lead Free Status
Vendor undefined
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M160ZE64I5N
Manufacturer:
ALTERA11
Quantity:
435
Part Number:
5M160ZE64I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–28. Global Clock External I/O Timing Parameters for the 5M570Z Device
Table 3–29. Global Clock External I/O Timing Parameters for the 5M1270Z Device
May 2011 Altera Corporation
t
t
t
t
t
t
t
t
f
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
t
t
t
t
t
t
t
t
f
Notes to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
(2) Not applicable to the F324 package of the 5M1270Z device.
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
Symbol
Symbol
clock input pin maximum frequency.
clock input pin maximum frequency.
Table
Table
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
3–28:
3–29:
Table 3–28
Table 3–29
Parameter
Parameter
lists the external I/O timing parameters for the 5M570Z device.
lists the external I/O timing parameters for the 5M1270Z device.
Condition
Condition
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
—
—
—
—
—
—
—
—
—
—
—
—
Min
253
253
2.2
2.0
5.4
—
—
—
Min
216
0
216
2.0
1.5
4.0
—
—
—
0
C4
C4
(Note 1)
184.1
(Note
Max
247.5
9.5
5.7
6.7
—
—
—
—
—
Max
8.1
4.8
5.9
—
—
—
—
—
1),
(2)
Min
339
339
4.4
2.0
8.4
—
—
—
Min
0
266
266
1.9
2.0
5.0
—
—
—
0
C5, I5
C5, I5
MAX V Device Handbook
118.3
17.7
Max
8.5
8.7
201.1
—
—
—
—
—
Max
10.0
5.9
7.3
—
—
—
—
—
MHz
Unit
ns
ns
ns
ns
ns
ps
ps
ns
MHz
Unit
3–21
ns
ns
ns
ns
ns
ps
ps
ns