EP4S100G3F45I1N Altera Corporation, EP4S100G3F45I1N Datasheet - Page 5

• Manufacturer Part Number: EP4S100G3F45I1N
• Description: IC STRATIX IV FPGA 290K 1932FBGA
• Manufacturer: Altera Corporation
• Series: STRATIX® IV GTr

Specifications of EP4S100G3F45I1N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17661952
• Number Of I /o: 781
• Number Of Gates: -
• Voltage - Supply: 0.92 V ~ 0.98 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1932-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
June 2011 Altera Corporation
Stratix IV GT Devices
1
1
Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:
■
■
The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to
on page
For more information about Stratix IV GT devices and transceiver architecture, refer
to the
Figure 1–3
Figure 1–3. Stratix IV GT Chip View
Note to
(1) Resource counts vary with device selection, package selection, or both.
Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA
circuitry and support data rates between 600 Mbps and 11.3 Gbps
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
Figure
Transceiver Architecture in Stratix IV Devices
1–16.
shows a high-level Stratix IV GT chip view.
1–3:
General Purpose I/O and
PLL
PLL
PLL
PLL
with DPA and Soft CDR
High-Speed LVDS I/O
Transceiver Block
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
(Note 1)
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
FPGA Fabric
PLL PLL
PLL PLL
600 Mbps-11.3 Gbps CDR-based Transceiver
General Purpose I/O and up to 1.6 Gbps
LVDS interface with DPA and Soft-CDR
chapter.
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
Stratix IV Device Handbook Volume 1
PLL
PLL
PLL
PLL
Table 1–7
1–5