EP4SE530H35I4N Altera Corporation, EP4SE530H35I4N Datasheet - Page 54
EP4SE530H35I4N
Manufacturer Part Number
EP4SE530H35I4N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera Corporation
Series
STRATIX® IV Er
Datasheet
1.EP4SGX70DF29C4N.pdf
(80 pages)
Specifications of EP4SE530H35I4N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
28033024
Number Of I /o
744
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-BBGA Exposed Pad
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
EP4SE530H35I4N
Manufacturer:
SAMSUNG
Quantity:
1 000
Company:
Part Number:
EP4SE530H35I4N
Manufacturer:
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1–46
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Core Performance Specifications
f
1
Transceiver Datapath PCS Latency
For more information about:
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This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn)
specifications.
Clock Tree Specifications
Table 1–33
Table 1–33. Clock Tree Performance for Stratix IV Devices—Preliminary
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
Global clock and
Regional clock
Periphery clock
Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the
Architecture in Stratix IV Devices
PCIe mode PCS latency, refer to Figure 1-102 in the
Stratix IV Devices
XAUI mode PCS latency, refer to Figure 1-119 in the
Stratix IV Devices
GIGE mode PCS latency, refer to Figure 1-128 in the
Stratix IV Devices
SONET/SDH mode PCS latency, refer to Figure 1-136 in the
Architecture in Stratix IV Devices
SDI mode PCS latency, refer to Figure 1-141 in the
IV Devices
(OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the
Architecture in Stratix IV Devices
Symbol
lists the clock tree specifications for Stratix IV devices.
chapter.
–2/–2× Speed Grade
chapter.
chapter.
chapter.
800
550
Performance
chapter.
chapter.
chapter.
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
–3 Speed Grade
700
500
Transceiver Architecture in Stratix
Transceiver Architecture in
Transceiver Architecture in
Transceiver Architecture in
–4 Speed Grade
December 2011 Altera Corporation
Transceiver
500
450
Transceiver
Switching Characteristics
Transceiver
MHz
MHz
Unit