EP2AGX95EF35I3N Altera Corporation, EP2AGX95EF35I3N Datasheet - Page 64

• Manufacturer Part Number: EP2AGX95EF35I3N
• Description: IC ARRIA II GX FPGA 95K 1152FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX95EF35I3N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6839296
• Number Of I /o: 452
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

1–56
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 2 of 2)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
t
f
t
t
t
t
t
t
t
t
f
Notes to
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
(2) This specification is limited by the lower of the two: I/O F
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
(4) F
(5) Peak-to-peak jitter with a probability level of 10
(6) The cascaded PLL specification is only applicable with the following condition:
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) External memory interface clock output jitter specifications use a different measurement method, which is available in
DLOCK
CLBW
PLL_PSERR
ARESET
INCCJ
OUTPJ_DC
OUTCCJ_DC
OUTPJ_IO
(8)
OUTCCJ_IO
(8)
CASC_OUTPJ_DC
(5),
DRIFT
Symbol
standard.
than 120 ps.
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in
a. Upstream PLL: 0.59 Mhz  Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
page
REF
(6)
(3),
Table
is fIN/N when N = 1.
1–71.
(5),
(5)
(5),
(5)
(4)
1–45:
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
Accuracy of PLL phase shift
Minimum pulse width on the areset signal
Input clock cycle to cycle jitter (F
Input clock cycle to cycle jitter (F
Period Jitter for dedicated clock output (F
Period Jitter for dedicated clock output (F
Cycle to Cycle Jitter for dedicated clock output
(F
Cycle to Cycle Jitter for dedicated clock output
(F
Period Jitter for clock output on regular I/O
(F
Period Jitter for clock output on regular I/O
(F
Cycle to Cycle Jitter for clock output on regular I/O
(F
Cycle to Cycle Jitter for clock output on regular I/O
(F
Period Jitter for dedicated clock output in cascaded PLLs
(F
Period Jitter for dedicated clock output in cascaded PLLs
(F
Frequency drift after PFDENA is disabled for duration of
100 us
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
≥ 100 MHz)
≥ 100 MHz)
< 100 MHz)
< 100 MHz)
≥ 100 MHz)
< 100 MHz)
< 100MHz)
≥100MHz)
Parameter
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
Table 1–64 on page
REF
REF
(7)
MAX
< 100 MHz)
≥ 100 MHz)
or F
OUT
OUT
OUT
≥ 100 MHz)
< 100 MHz)
of the PLL.
1–71.
Min
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—
—
—
10
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—
—
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Chapter 1: Device Datasheet for Arria II Devices
Typ
0.3
1.5
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—
—
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4
December 2011 Altera Corporation
±750
Max
0.15
17.5
17.5
±50
175
175
600
600
250
±10
—
—
—
—
60
60
25
1
Switching Characteristics
Table 1–63 on
mUI (p-p)
mUI (p-p)
mUI (p-p)
mUI (p-p)
mUI (p-p)
UI (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
ps (p-p)
MHz
MHz
MHz
Unit
ms
ps
ns
%