EP2AGX95EF29C5 Altera Corporation, EP2AGX95EF29C5 Datasheet - Page 75
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EP2AGX95EF29C5
Manufacturer Part Number
EP2AGX95EF29C5
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera Corporation
Series
Arria II GXr
Datasheet
1.EP2AGX95EF35C5N.pdf
(90 pages)
Specifications of EP2AGX95EF29C5
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6839296
Number Of I /o
372
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-BBGA
Lead Free Status
Contains lead
Rohs Status
RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–55. DPA Lock Time Specifications for Arria II Devices
Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for All Arria II GX Devices and for Arria II GZ
Devices at a Data Rate less than 1.25 Gbps
December 2011 Altera Corporation
Miscellaneous
Notes to
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in the table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Sinusoidal Jitter Amplitude (UI)
Standard
Table
P-P
0.1
1–55:
Figure 1–5
Arria II GZ devices at a data rate less than 1.25 Gbps and all the Arria II GX devices.
Training Pattern
10101010
01010101
shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
20db/dec
Transitions in One
Repetition of the
Training Pattern
Number of Data
baud/1667
8
8
(Note
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
1), (2),
(3)
Repetitions per
Transitions
(Part 2 of 2)
Number of
256 Data
20,000,000
32
32
(4)
Jitter Frequency (Hz)
640 data transitions
640 data transitions
Maximum
1–67