EP2AGX65DF25I5 Altera Corporation, EP2AGX65DF25I5 Datasheet - Page 62

• Manufacturer Part Number: EP2AGX65DF25I5
• Description: IC ARRIA II GX FPGA 65K 572FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX65DF25I5

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5371904
• Number Of I /o: 252
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 572-FBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

1–54
Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
f
f
t
t
t
f
f
t
t
f
t
t
f
t
t
OUT
OUT_EXT
OUTDUTY
OUTPJ_DC
OUTCCJ_DC
OUTPJ_IO
OUTCCJ_IO
CONFIGPLL
CONFIGPHASE
SCANCLK
LOCK
DLOCK
CL B W
PLL_PSERR
ARESET
Symbol
Output frequency for internal global or regional clock
(–4 Speed Grade)
Output frequency for internal global or regional clock
(–5 Speed Grade)
Output frequency for internal global or regional clock
(–6 Speed Grade)
Output frequency for external clock output (–4 Speed Grade)
Output frequency for external clock output (–5 Speed Grade)
Output frequency for external clock output (–6 Speed Grade)
Duty cycle for external clock output (when set to 50%)
Dedicated clock output period jitter (f
Dedicated clock output period jitter (f
Dedicated clock output cycle-to-cycle jitter (f
Dedicated clock output cycle-to-cycle jitter (f
Regular I/O clock output period jitter (f
Regular I/O clock output period jitter (f
Regular I/O clock output cycle-to-cycle jitter (f
Regular I/O clock output cycle-to-cycle jitter (f
Time required to reconfigure PLL scan chains
Time required to reconfigure phase shift
SCANCLK frequency
Time required to lock from end of device configuration
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
Accuracy of PLL phase shift
Minimum pulse width on areset signal
Description
OUT
OUT
OUT
OUT
 100 MHz)
 100 MHz)
 100 MHz)
 100 MHz)
OUT
OUT
OUT
OUT
 100 MHz)
 100 MHz)
 100 MHz)
 100 MHz)
Min
—
—
—
—
—
—
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
Chapter 1: Device Datasheet for Arria II Devices
Typ
3.5
0.3
1.5
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
—
—
—
—
—
1
4
December 2011 Altera Corporation
670
622
500
Max
500
500
400
300
300
650
650
100
±50
55
30
30
65
65
—
—
—
—
—
—
Switching Characteristics
1
1
(5)
(5)
(5)
mUI (p–p)
mUI (p–p)
mUI (p–p)
mUI (p–p)
SCANCLK
SCANCLK
ps (p–p)
ps (p–p)
ps (p–p)
ps (p–p)
cycles
cycles
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ms
ps
ns
%