EP2AGX65DF25C5 Altera Corporation, EP2AGX65DF25C5 Datasheet - Page 72

• Manufacturer Part Number: EP2AGX65DF25C5
• Description: IC ARRIA II GX FPGA 65K 572FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX65DF25C5

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5371904
• Number Of I /o: 252
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 572-FBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

1–64
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 4 of 4)
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
f
Soft-CDR PPM
tolerance
DPA run length
Sampling
window (SW)
Notes to
(1) f
(2) This applies to interfacing with DPA receivers. For interfacing with non-DPA receivers, the maximum supported data rate is 945 Mbps. Beyond
(3) The minimum and maximum specification depends on the clock source (for example, PLL and clock pin) and the clock routing resource you
(4) The specification is only applicable under the influence of core noise.
(5) Specification is only applicable for true LVDS using dedicated SERDES.
(6) Dedicated SERDES and DPA features are only available on the right banks.
(7) You are required to calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board
Clock
f
frequency) true
differential I/O
standards
f
frequency) single
ended I/O standards
f
frequency) single
ended I/O standards
f
clock frequency)
HSDR
HSCLK_in
HSCLK_in
(9)
HSCLK_in
(10)
HSCLK_OUT
840 Mbps, PCB trace compensation is required. PCB trace compensation refers to the adjustment of the PCB trace length for LVDS channels
to improve channel-to-channel skews and is required to support date rates beyond 840 Mbps.
use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate.
skew margin, transmitter channel-to-channel skew, and the receiver sampling margin to determine the leftover timing margin.
HSCLK_IN
Symbol
(data rate)
Symbol
Table
(input clock
(input clock
(input clock
(output
= f
1–53:
HSDR
/ W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate.
Non-DPA mode
SERDES factor
SERDES factor
DDR registers)
SERDES factor
SDR registers)
J = 2 (using
J = 1 (using
Conditions
J = 3 to 10
DPA mode
Soft-CDR
Table 1–54
mode
Clock boost factor
Clock boost factor
Clock boost factor
(5)
W = 1 to 40
W = 1 to 40
W = 1 to 40
Conditions
—
lists the high-speed I/O timing for Arria II GZ devices.
Min
(3)
(3)
(3)
(3)
(3)
(3)
—
—
—
I3
10,000
Max
945
300
300
(7)
(7)
(7)
Min
5
5
5
5
Min
—
—
—
(3)
(3)
(3)
C3, I3
Typ
—
—
—
—
C4
10,000
(Note 1), (2), (10)
Max
945
300
300
(7)
(7)
(7)
717
Max
717
717
420
(7)
Min
—
—
—
(3)
(3)
(3)
Chapter 1: Device Datasheet for Arria II Devices
C5,I5
Min
5
5
5
5
10,000
(Part 1 of 3)
Max
740
300
350
(7)
(7)
(7)
December 2011 Altera Corporation
C4, I4
Typ
—
—
—
—
Min
—
—
—
(3)
(3)
(3)
Switching Characteristics
C6
717
Max
717
717
420
10,000
Max
640
300
400
(7)
(7)
(7)
(7)
PPM
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
Unit
Unit
UI
ps