EP4CGX75DF27I7 Altera Corporation, EP4CGX75DF27I7 Datasheet - Page 40
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EP4CGX75DF27I7
Manufacturer Part Number
EP4CGX75DF27I7
Description
IC CYCLONE IV GX FPGA 75K 672FBG
Manufacturer
Altera Corporation
Series
CYCLONE® IV GXr
Datasheet
1.EP4CE15F23C7N.pdf
(44 pages)
Specifications of EP4CGX75DF27I7
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BGA
Lead Free Status
Contains lead
Rohs Status
RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27I7N
Manufacturer:
ALCAYME
Quantity:
201
Company:
Part Number:
EP4CGX75DF27I7N
Manufacturer:
ALTERA
Quantity:
748
Part Number:
EP4CGX75DF27I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–40
Table 1–46. Glossary (Part 3 of 5)
Cyclone IV Device Handbook,
Volume 3
Letter
R
S
R
Receiver Input
Waveform
Receiver input
skew margin
(RSKM)
Single-ended
voltage-
referenced I/O
Standard
SW (Sampling
Window)
L
Term
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver input waveform for LVDS and LVPECL differential standards:
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V
V
OH
OL
V
CM
V
ID
V
ID
Definitions
V
REF
Chapter 1: Cyclone IV Device Datasheet
V
ID
November 2011 Altera Corporation
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0 V
p - n
V
V
IH(DC)
IL(DC)
V
V
IH ( AC )
IL(AC )
V
CCIO
V
IH
IL
Glossary
SS