EP4CGX30CF23I7N Altera Corporation, EP4CGX30CF23I7N Datasheet - Page 40

no-image

EP4CGX30CF23I7N

Manufacturer Part Number
EP4CGX30CF23I7N
Description
IC CYCLONE IV GX FPGA 30K 484FBG
Manufacturer
Altera Corporation
Series
CYCLONE® IV GXr
Datasheet

Specifications of EP4CGX30CF23I7N

Number Of Logic Elements/cells
29440
Number Of Labs/clbs
1840
Total Ram Bits
1105920
Number Of I /o
290
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BGA
Lead Free Status
Lead free
Rohs Status
RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX30CF23I7N
Manufacturer:
TOSHIBA
Quantity:
2 000
Part Number:
EP4CGX30CF23I7N
Manufacturer:
ALTERA21
Quantity:
155
Part Number:
EP4CGX30CF23I7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP4CGX30CF23I7N
Manufacturer:
ALTERA
0
1–40
Table 1–46. Glossary (Part 3 of 5)
Cyclone IV Device Handbook,
Volume 3
Letter
R
S
R
Receiver Input
Waveform
Receiver input
skew margin
(RSKM)
Single-ended
voltage-
referenced I/O
Standard
SW (Sampling
Window)
L
Term
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver input waveform for LVDS and LVPECL differential standards:
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V
V
OH
OL
V
CM
V
ID
V
ID
Definitions
V
REF
Chapter 1: Cyclone IV Device Datasheet
V
ID
November 2011 Altera Corporation
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0 V
p - n
V
V
IH(DC)
IL(DC)
V
V
IH ( AC )
IL(AC )
V
CCIO
V
IH
IL
Glossary
SS

Related parts for EP4CGX30CF23I7N