EP4CE40F29C6N Altera Corporation, EP4CE40F29C6N Datasheet
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EP4CE40F29C6N
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice ...
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... Chapter 1: Cyclone IV Device Datasheet Operating Conditions Table 1–1 lists the absolute (1) —Preliminary Min Max Unit –0.5 1.8 V –0.5 3.75 V –0.5 1.8 V –0.5 3.9 V –0.5 3.9 V –0.5 2.625 V –0.5 2.625 V –0.5 1.8 V –0.5 3.95 V – –65 150 °C –40 125 °C Table 1–2 and November 2011 Altera Corporation ...
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... I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations in which the device idle state, lifetimes are increased. Figure 1–1. Cyclone IV Devices Overshoot Duration November 2011 Altera Corporation Condition (V) Overshoot Duration High Time ...
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... V 1.71 1.8 1.89 V 1.425 1.5 1.575 V 1.14 1.2 1.26 V 2.375 2.5 2.625 V 1.15 1.2 1.25 V 0.97 1.0 1.03 V –0.5 — 3 — CCIO 0 — 85 °C –40 — 100 °C –40 — 125 °C –40 — 125 °C 50 µs — — 50 µs — — November 2011 Altera Corporation ...
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... V CC_CLKIN (3), (5), (6) Differential clock input pins power supply for 1 operation Differential clock input pins power supply for 1 operation Differential clock input pins power supply for 1 operation November 2011 Altera Corporation (1), (2) (Part Conditions — Conditions — — — — — ...
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... I/O Banks 3, 8, and 9 where CCIO level of I/O CCIO Table 1–5 lists the Unit ± 2000 V ± 1000 V ± 500 V ± 250 V November 2011 Altera Corporation ...
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... Bus hold low < V < V — IN CCIO overdrive current Bus hold high < V < V — IN CCIO overdrive current November 2011 Altera Corporation (1), (2) Conditions Device — I CCIOMAX — O CCIOMAX - (1) —Preliminary V (V) CCIO 1 ...
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... Chapter 1: Cyclone IV Device Datasheet Operating Conditions 2.5 3.0 3.3 Unit Max Min Max Min Max 1.7 0.8 2 0.8 2 Industrial, Extended Unit industrial, and Automotive Maximum ±40 % ±40 % ±50 % ±50 % ±50 % Industrial, Extended Unit industrial, and Automotive Maximum ±10 % ±10 % ±10 % ±10 % ±10 % November 2011 Altera Corporation V ...
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... V is final voltage. 2 (12 the initial voltage. 1 November 2011 Altera Corporation Table 1–10 dR/dT (%/°C) 0.262 0.234 0.219 0.199 0.161 ...
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... Operating Conditions Typical – Typical – Typical – Quad Flat Quad Flat Fineline Unit Pack No Leads BGA (QFP) (QFN) (FBGA ( because of higher pin CO November 2011 Altera Corporation ...
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... The I/O ramp rate more. For ramp rates faster than 10 ns, |IIOPIN dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. 1 During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF. November 2011 Altera Corporation Conditions (2), ( 3.3 V ± ...
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... CCIO 0.45 2 0.45 0. CCIO CCIO 0. CCIO CCIO 0 1.5 CCIO CCIO 0 1.5 CCIO CCIO “Glossary” on page 1–38. AN 447: Interfacing Cyclone III November 2011 Altera Corporation (mA) –4 –2 –4 –0.1 –1 –2 –2 –2 –0.5 –0.5 ...
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... Class II 0.1 0.1 HSTL - 12 V – REF REF –0.15 Class I 0.08 0.08 HSTL - 12 V – REF REF –0.15 Class II 0.08 0.08 November 2011 Altera Corporation V (V) REF Min Typ 1.19 1.25 0.833 0.9 0.969 0.85 0.9 0.71 0.75 (3) ( CCIO CCIO (4) ( CCIO CCIO 1–16, refer to “Glossary” on page 1– ...
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... Max Min Typ Max Min 1.80 1.80 — — — — 1.55 1.80 1.80 — — — — 1.55 1.80 1.80 247 — 600 1.125 1.55 November 2011 Altera Corporation Max V /2 CCIO + 0.125 V /2 CCIO + 0.125 (V) DIF(AC) Max — — 0. CCIO (3) V (V) OS Typ Max — — — ...
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... The PowerPlay power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, combined with detailed circuit models, can yield very accurate power estimates. November 2011 Altera Corporation (1) (2) V ...
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... There are no designations on finalized tables. Cyclone IV Device Handbook, Volume 3 PowerPlay Power Analysis chapter in volume 3 of the Quartus II Chapter 1: Cyclone IV Device Datasheet Switching Characteristics Early Power Estimator November 2011 Altera Corporation ...
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... Delta time between — reconfig_clk Transceiver block minimum — power-down pulse width Receiver 1.4 V PCML, Supported I/O 1.5 V PCML, Standards 2.5 V PCML, LVPECL, LVDS November 2011 Altera Corporation C6 C7, I7 Min Typ Max Min Typ 1.2 V PCML, 1.5 V PCML, 3.3 V PCML, Differential LVPECL, LVDS, HCSL 50 — 156.25 50 — 30 — ...
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... November 2011 Altera Corporation Unit Mbps Mbps — ppm ppm ppm µs µs ns ...
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... Serial Rapid I/O common mode SR, SDI, XAUI, return loss SATA Rise time — Fall time — Intra-differential pair — skew Intra-transceiver — block skew November 2011 Altera Corporation C6 C7, I7 Min Typ Max Min Typ — — 4000 — — — — 4000 — ...
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... Minimum is 2 parallel clock cycles (Figure Chapter 1: Cyclone IV Device Datasheet Switching Characteristics C8 Max Min Typ Max 125 25 — 125 156.25 25 — 156.25 1–2), or after rx_freqlocked signal goes high in November 2011 Altera Corporation Unit MHz MHz ...
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... Figure 1–3 shows the lock time parameters in automatic mode. Figure 1–3. Lock Time Parameters for Automatic Mode Reset Signals rx _ analogreset rx _ digitalreset Two parallel clock cycles Output Status Signals 1 busy rx _ freqlocked November 2011 Altera Corporation 2 t LTD_Manual 3 t LTR_LTD_Manual ( ...
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... Tx term that equals 100 Setting (mV 600 800 Chapter 1: Cyclone IV Device Datasheet Switching Characteristics Positive Channel (p) Negative Channel (n) Ground p − Positive Channel (p) Negative Channel (n) Ground p − ( 900 1000 1200 November 2011 Altera Corporation ...
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... Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 1 of 2)—Preliminary Device C6 C7 EP4CE6 500 437.5 EP4CE10 500 437.5 EP4CE15 500 437.5 EP4CE22 500 437.5 EP4CE30 500 437.5 EP4CE40 500 437.5 November 2011 Altera Corporation (1), (2) —Preliminary C6 C7, I7 Min Typ Max Min Typ — — 0.25 — — > 0.6 > 0.6 — — 0.14 — ...
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... MHz 40 — — — 0.15 UI — — ±750 ps — — 472.5 MHz — — 472.5 MHz — — 450 MHz — — 402.5 MHz — — 362 MHz — — 265 MHz — — November 2011 Altera Corporation ...
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... Upstream PLL—0.59 MHz Upstream PLL bandwidth < 1 MHz ■ Downstream PLL—Downstream PLL bandwidth > 2 MHz ■ (9) PLL cascading is not supported for transceiver applications. November 2011 Altera Corporation (1), (2) (Part 2 of 2)—Preliminary Parameter 100 MHz) 100 MHz) – ...
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... C8L, I8L C9L 274 238 200 157 MHz 274 238 200 157 MHz 274 238 200 157 MHz 274 238 200 157 MHz (1) DCLK f Unit MAX 66 MHz 133 MHz 66 MHz 100 MHz Configuration and Remote MAX November 2011 Altera Corporation for ...
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... PCI/PCI-X bus interface. I/Os using the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with load. November 2011 Altera Corporation DCLK Range ( ...
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... November 2011 Altera Corporation Unit MHz MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps — ps — ...
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... C = RISE LOAD – 80%, t — 500 C = FALL LOAD 5 pF November 2011 Altera Corporation (1), (2), (4) C7, I7 C8, A7 Max Min Typ Max 1 — — 1 — — C7, I7 C8, A7 Max Min Typ Max Min Typ Max Min Typ ...
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... November 2011 Altera Corporation Unit ms Unit Max MHz MHz MHz MHz MHz 265 MHz 265 Mbps 265 Mbps 265 Mbps 265 Mbps ...
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... LOCK (3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades. November 2011 Altera Corporation (1), (2), C7, I7 ...
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... MHz 320 10 250 MHz 320 10 250 MHz 320 10 250 MHz 320 10 250 MHz 362 10 265 MHz 640 100 500 Mbps 640 80 500 Mbps 640 70 500 Mbps 640 40 500 Mbps 640 20 500 Mbps 362 10 265 Mbps November 2011 Altera Corporation ...
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... Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard. (2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global clock (GCLK) network. November 2011 Altera Corporation (1), (3) (Part 2 of 2)—Preliminary ...
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... Chapter 1: Cyclone IV Device Datasheet Switching Characteristics C9L Unit Max Min Max Maximum Units 20 µs (1), (2) Max Offset Slow Corner Unit I8L C8L C9L I8L 1.924 3.387 4.017 3.411 ns 1.875 3.341 4.252 3.367 ns 0.631 1.111 1.377 1.124 ns November 2011 Altera Corporation ...
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... Input delay from pin to dataout to internal cells core Input delay from pin to Pad to I/O input register input register I/O output Delay from output register to register to output pin pad November 2011 Altera Corporation Number Min of Fast Corner Offset Setting C8L 12 0 0.971 Number Min ...
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... Max Offset Slow Corner (1), (2) —Preliminary Max Offset Slow Corner (1), (2) (Part 1 of 2)—Preliminary Max Offset Slow Corner Unit 2.184 2.336 2.451 2.387 ns 2.200 2.399 2.554 2.446 ns November 2011 Altera Corporation Unit ns Unit ...
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... The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software November 2011 Altera Corporation Number Min ...
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... High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI). Input Waveforms for the SSTL I V SWING Differential I/O Standard Cyclone IV Device Handbook, Volume 3 Chapter 1: Cyclone IV Device Datasheet Cyclone IV Devices Definitions — — — — — REF V IL November 2011 Altera Corporation I/O Timing ...
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... Captured Signal to be Driven K — L — M — N — O — The following highlights the PLL specification parameters: CLK Core Clock P PLL Block Key Q — November 2011 Altera Corporation Definitions t t JCP JPSU_TDI JCH JCL JPSU_TMS t t JPZX JPCO t t JSSU JSH t t ...
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... The setup and hold times determine the ideal strobe position in the sampling window. Cyclone IV Device Handbook, Volume 3 Definitions REF V OL Chapter 1: Cyclone IV Device Datasheet Glossary Positive Channel ( Negative Channel ( Ground CCIO IH(DC) V IL(DC) V IL( November 2011 Altera Corporation ...
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... Waveform Differential Waveform (Mathematical Function of Positive & Negative Channel) t Signal low-to-high transition time (20–80%). RISE t Input register setup time — November 2011 Altera Corporation Definitions variation and clock skew. The clock is included in the TCCS measurement — ...
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... AC differential input cross point voltage: The voltage at which the differential input signals must V X (AC) cross. W — X — Y — Z — Cyclone IV Device Handbook, Volume 3 Chapter 1: Cyclone IV Device Datasheet Definitions = ( must not exceed REF REF(DC) — — — — Glossary = V – noise. The REF(AC) REF(DC) November 2011 Altera Corporation ...
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... Updated to include automotive devices: ■ ■ March 2010 1.2 ■ ■ ■ ■ February 2010 1.1 ■ November 2009 1.0 Initial release. November 2011 Altera Corporation Changes Updated “Maximum Allowed Overshoot or Undershoot Conditions”, and “PLL Specifications” sections. Updated Table 1–2, Table 1–3, Table 1–4, Table 1– ...
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... Cyclone IV Device Handbook, Volume 3 Chapter 1: Cyclone IV Device Datasheet Document Revision History November 2011 Altera Corporation ...