EP4CE15E22C7 Altera Corporation, EP4CE15E22C7 Datasheet - Page 23
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EP4CE15E22C7
Manufacturer Part Number
EP4CE15E22C7
Description
IC CYCLONE IV FPGA 15K 144EQFP
Manufacturer
Altera Corporation
Series
CYCLONE® IV Er
Datasheet
1.EP4CE15F23C7N.pdf
(44 pages)
Specifications of EP4CE15E22C7
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
81
Number Of Gates
-
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP Exposed Pad
Lead Free Status
Contains lead
Rohs Status
RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE15E22C7N
Manufacturer:
ALTERA
Quantity:
201
Part Number:
EP4CE15E22C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–23. Transceiver Block AC Specification for Cyclone IV GX Devices
Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 1 of 2)—Preliminary
November 2011 Altera Corporation
PCIe Transmit Jitter Generation
Total jitter at 2.5 Gbps
(Gen1)
PCIe Receiver Jitter Tolerance
Total jitter at 2.5 Gbps
(Gen1)
GIGE Transmit Jitter Generation
Deterministic jitter
(peak-to-peak)
Total jitter (peak-to-peak)
GIGE Receiver Jitter Tolerance
Deterministic jitter
tolerance (peak-to-peak)
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Notes to
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers specified are valid for the stated conditions only.
(3) The jitter numbers for PIPE are compliant to the PCIe Base Specification 2.0.
(4) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
EP4CE6
EP4CE10
EP4CE15
EP4CE22
EP4CE30
EP4CE40
Device
Description
Table
Symbol/
Core Performance Specifications
1–23:
500
500
500
500
500
500
C6
Table 1–23
The following sections describe the clock tree specifications, PLLs, embedded
multiplier, memory block, and configuration specifications for Cyclone IV Devices.
Clock Tree Specifications
Table 1–24
Compliance pattern
Compliance pattern
Pattern = CRPAT
Pattern = CRPAT
Pattern = CJPAT
Pattern = CJPAT
437.5
437.5
437.5
437.5
437.5
437.5
C7
Conditions
(3)
(4)
(3)
(4)
lists the Cyclone IV GX transceiver block AC specifications.
lists the clock tree specifications for Cyclone IV devices.
402
402
402
402
402
402
C8
Min
—
—
—
C8L
362
362
362
362
362
362
> 0.66
Performance
> 0.6
> 0.4
Typ
—
—
—
C6
(1)
0.279
0.25
0.14
Max
C9L
265
265
265
265
265
265
(1)
Min
—
—
—
(1),
(2)
> 0.66
C7, I7
Typ
437.5
437.5
437.5
437.5
437.5
437.5
> 0.6
> 0.4
—
—
—
—Preliminary
I7
0.279
Max
0.25
0.14
I8L
362
362
362
362
362
362
Min
—
—
—
(1)
Cyclone IV Device Handbook,
> 0.66
Typ
> 0.6
> 0.4
—
—
—
C8
402
402
402
402
402
402
A7
0.279
Max
0.25
0.14
Volume 3
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
UI
UI
UI
UI
UI
UI
1–23