EP4CE6E22C8LN Altera Corporation, EP4CE6E22C8LN Datasheet - Page 38
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EP4CE6E22C8LN
Manufacturer Part Number
EP4CE6E22C8LN
Description
IC CYCLONE IV FPGA 6K 144EQFP
Manufacturer
Altera Corporation
Series
CYCLONE® IV Er
Datasheet
1.EP4CE15F23C7N.pdf
(44 pages)
Specifications of EP4CE6E22C8LN
Number Of Logic Elements/cells
6272
Number Of Labs/clbs
392
Total Ram Bits
276480
Number Of I /o
91
Number Of Gates
-
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP Exposed Pad
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE6E22C8LN
Manufacturer:
ALTERA
Quantity:
240
1–38
I/O Timing
Glossary
Table 1–46. Glossary (Part 1 of 5)
Cyclone IV Device Handbook,
Volume 3
Letter
D
G
H
A
B
C
E
F
I
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
HSCLK
f
Term
—
—
—
—
—
Use the following methods to determine I/O timing:
■
■
The Excel-based I/O timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
The Excel-based I/O Timing spreadsheet is downloadable from
Literature
Table 1–46
the Excel-based I/O Timing
the Quartus II timing analyzer
V
High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
Input pin to Global Clock network through the PLL.
High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
SWING
website.
lists the glossary for this chapter.
Definitions
—
—
—
—
—
Chapter 1: Cyclone IV Device Datasheet
November 2011 Altera Corporation
Cyclone IV Devices
V
V
V
REF
IH
IL
I/O Timing