LT1719CS6#TRMPBF Linear Technology, LT1719CS6#TRMPBF Datasheet - Page 9

• Manufacturer Part Number: LT1719CS6#TRMPBF
• Description: IC COMP R-RINOUT SINGLE SOT23-6
• Manufacturer: Linear Technology
• Series: UltraFast™r
• Type: General Purposer

Specifications of LT1719CS6#TRMPBF

• Number Of Elements: 1
• Output Type: CMOS, Rail-to-Rail, TTL
• Voltage - Supply: 2.7 V ~ 6 V
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Comparator Type: General Purpose
• No. Of Comparators: 1
• Response Time: 4.5ns
• Ic Output Type: CMOS, TTL
• Output Compatibility: CMOS, TTL
• Supply Current: 4.6mA
• Supply Voltage Range: 2.7V To 6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LT1719CS6#TRMPBFTR

APPLICATIONS
equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection cir-
cuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltage is at the absolute
maximum rating.
The LT1719 input stage has general purpose internal ESD
protection for the human body model. For use as a line
receiver, additional external protection may be required.
As with most integrated circuits, the level of immunity to
ESD is much greater when residing on a printed circuit
board where the power supply decoupling capacitance will
limit the voltage rise caused by an ESD pulse.
Input Bias Current
Input bias current is measured with both inputs held at 1V.
As with any PNP differential input stage, the LT1719 bias
current flows out of the device. It will go to zero on the
higher of the two inputs and double on the lower of the two
inputs. With more than two diode drops of differential
input voltage, the LT1719’s input protection circuitry
activates, and current out of the lower input will increase
an additional 30% and there will be a small bias current
into the higher of the two input pins, of 4 A or less. See the
Typical Performance curve “Input Current vs Differential
Input Voltage.”
High Speed Design Considerations
Application of high speed comparators is often plagued by
oscillations. The LT1719 has 4mV of internal hysteresis,
which will prevent oscillations as long as parasitic output
to input feedback is kept below 4mV. However, with the
2V/ns slew rate of the LT1719 outputs, a 4mV step can be
created at a 100 input source with only 0.02pF of output
to input coupling. The LT1719’s pinout has been arranged
to minimize problems by placing the sensitive inputs away
from the outputs, shielded by the power rails. The input
and output traces of the circuit board should also be
separated, and the requisite level of isolation is readily
achieved if a topside ground plane runs between the
output and the inputs. For multilayer boards where the
ground plane is internal, a topside ground or supply trace
should be run between the inputs and the output.
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INFORMATION
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Figure 2 shows a typical topside layout of the LT1719S8 on
such a multilayer board. Shown is the topside metal etch
including traces, pin escape vias, and the land pads for an
SO-8 LT1719 and its adjacent X7R 10nF bypass capacitors
in the 1206 case. The same principles should be used with
the SOT 23-6.
The ground trace from Pin 5 runs under the device up to
the bypass capacitor, shielding the inputs from the
outputs. Note the use of a common via for the LT1719 and
the bypass capacitors, which minimizes interference from
high frequency energy running around the ground plane or
power distribution traces.
The supply bypass should include an adjacent
10nF ceramic capacitor and a 2.2 F tantalum capacitor no
farther than 5cm away; use more capacitance on + V
driving more than 4mA loads. To prevent oscillations, it is
helpful to balance the impedance at the inverting and
noninverting inputs; source impedances should be kept
low, preferably 1k or less.
The outputs of the LT1719 are capable of very high slew
rates. To prevent overshoot, ringing and other problems
with transmission line effects, keep the output traces
shorter than 10cm, or be sure to terminate the lines to
maintain signal integrity. The LT1719 can drive DC termi-
nations of 200 or more, but lower characteristic imped-
ance traces can be used with series termination or AC
termination topologies.
Shutdown Control
The LT1719 features a shutdown control pin for reduced
quiescent current when the comparator is not needed.
During shutdown, the inputs and the outputs become high
impedances. The LT1719 is enabled when the shutdown
input is pulled low with a threshold roughly two diode
drops below + V
TTL gate, a pull-up resistor should be used. Because
Figure 2. Typical Topside Metal for Multilayer PCB Layouts
S
or V
+
. Therefore, if driven by a standard
1719 F02
LT1719
9
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if