HA9P4905-5Z Intersil, HA9P4905-5Z Datasheet - Page 4
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HA9P4905-5Z
Manufacturer Part Number
HA9P4905-5Z
Description
IC COMPARATOR QUAD PREC 16-SOIC
Manufacturer
Intersil
Type
General Purposer
Datasheet
1.HA9P4905-5Z.pdf
(8 pages)
Specifications of HA9P4905-5Z
Number Of Elements
4
Output Type
CMOS, Push-Pull
Voltage - Supply
5 V ~ 15 V, ±2.5 V ~ 7.5 V
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.50mm Width)
Comparator Type
Precision
No. Of Comparators
4
Response Time
130ns
Ic Output Type
Pull Up / Pull Down
Supply Current
7mA
Supply Voltage Range
5V To ± 15V
Amplifier Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HA9P4905-5Z
Manufacturer:
Intersil
Quantity:
40
Part Number:
HA9P4905-5Z
Manufacturer:
INTERSIL
Quantity:
20 000
Schematic Diagram
Applying the HA-4900 Series Comparators
Supply Connections
This device is exceptionally versatile in working with most
available power supplies. The voltage applied to the V+ and V-
terminals determines the allowable input signal range; while the
voltage applied to the V
swing. In systems where dual analog supplies are available,
these would be connected to V+ and V-, while the logic supply
and return would be connected to V
analog and logic supply commons can be connected together
at one point in the system, since the comparator is immune to
noise on the logic supply ground. A negative output swing may
be obtained by connecting V
supply. Bipolar output swings (15V
using dual supplies. In systems where only a single logic supply
is available (+5V to 15V), V+ and V
together to the positive supply while V- and V
grounded. If an input signal could swing negative with respect
the V- terminal, a resistor should be connected in series with
the input to limit input current to < 5mA since the C-B junction of
the input transistor would be forward biased.
Unused Inputs
Inputs of unused comparator sections should be tied to a
differential voltage source to prevent output “chatter.”
Crosstalk
Simultaneous high frequency operation of all other channels
in the package will not affect the output logic state of a given
channel, provided that its differential input voltage is
sufficient to define a given logic state (∆V
level or high impedance input lines should be shielded from
other signal sources to reduce crosstalk and interference.
200kΩ
BIAS 2
Q
R
1kΩ
PR
9D
20D
Q
1
3
BIAS 3 BIAS 4
Q
Q
1
4
Q
R
1kΩ
9C
20C
R
4kΩ
D
9
D
4B
4A
Q
R
1kΩ
9B
20B
L
D
+ and V
9A
Q
Q
Q
R
540Ω
Q
L
R
4kΩ
R
1kΩ
2
4C
5
+ to ground and V
16
BIAS 1
9A
10
20A
4
L
Q
- determines the output
11
P-P
LOGIC
LOGIC
+IN
Q
R
1kΩ
R
500Ω
, Max) may be obtained
10
D
21
1
45
+ may be connected
+ and V
IN
Q
Q
D
R
13kΩ
LOGIC
17
12
11A
≥ ±V
2
HA-4900, HA-4902, HA-4905
L
- to a negative
LOGIC
OS
Q
2.5kΩ
ONE FOURTH ONLY
Q
- are
R
1kΩ
18
13
Q
3
R
). Low
19
6
M
N1
-. The
Q
Q
R
2.5kΩ
1kΩ
14
20
7
Q
R
4
21
Q
22
Q
M
Power Supply Decoupling
Decouple all power supply lines with 0.01µF ceramic capacitors
to ground line located near the package to reduce coupling
between channels or from external sources.
Response Time
Fast rise time (<200ns) input pulses of several volts
amplitude may result in delay times somewhat longer than
those illustrated for 100mV steps. Operating speed is
optimized by limiting the maximum differential input voltage
applied, with resistor-diode clamping networks.
Typical Applications
Data Acquisition System
In this circuit the HA-4900 series is used in conjunction with
a D to A converter to form a simple, versatile, multi-channel
analog input for a data acquisition system. In operation the
processor first sends an address to the D to A, then the
processor reads the digital word generated by the
comparator outputs. To perform a simple comparison, the
processor sets the D to A to a given reference level, then
examines one or more comparator outputs to determine if
their inputs are above or below the reference. A window
comparison consists of two such cycles with 2 reference
levels set by the D to A. One way to digitize the inputs would
be for the processor to increment the D to A in steps. The D
to A address, as each comparator switches, is the digitized
level of the input. While stairstepping the D to A is slower
than successive approximation, all channels are digitized
during one staircase ramp.
360Ω
15
N2
R
-IN
5
M
Q
N3
Q
Q
16
23
7
R
19kΩ
Q
17
33
Q
Q
D
24
35
36
Q
Q
R
664Ω
37
25
18
R
5kΩ
Q
14
34
Q
Q
D
39
26
38
M
Q
N4
28
R
8kΩ
Q
11
30
Q
14kΩ
R
8kΩ
D
R
29
15
29B
24
Q
29A
Q
8kΩ
100Ω
R
100Ω
R
R
31
22
12
23
M
N5
V
V
LOGIC
M
LOGIC
Q
N6
OUT
32
V+
V-
+
-