LM1973MX/NOPB National Semiconductor, LM1973MX/NOPB Datasheet - Page 8

• Manufacturer Part Number: LM1973MX/NOPB
• Description: IC AUDIO ATTENUATR W/MUTE 20SOIC
• Manufacturer: National Semiconductor
• Type: Audio Attenuatorr

Specifications of LM1973MX/NOPB

• Applications: Consoles, MIDI
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Pin Count: 20
• Screening Level: Commercial
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM1973MX; *LM1973MX/NOPB; LM1973MX

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Application Information
µPot SYSTEM ARCHITECTURE
The µPot’s digital interface is essentially a shift register,
where serial data is shifted in, latched, and then decoded. As
new data is shifted into the DATA-IN pin, the previously
latched data is shifted out the DATA-OUT pin. Once the data
is shifted in, the LOAD/SHIFT line goes high, latching in the
MSB: LSB
TABLE 1. LM1973 Micropot Attenuator
0000 0000
0000 0001
0000 0010
0000 0000
0000 0001
0000 0010
0000 0011
0010 0000
0010 0001
0010 0010
0100 0000
0100 0001
0100 0010
0100 1100
0100 1101
0101 0000
0001 1110
0100 1110
0001 1111
0011 1110
0011 1111
0100 1111
Contents
1111 1110
1111 1111
: : : : :
: : : : :
: : : : :
: : : : :
Address Register (Byte 0)
Register Set Description
Data Register (Byte 1)
Attenuation Level dB
100.0 (Mute)
100.0 (Mute)
100.0 (Mute)
100.0 (Mute)
Channel 1
Channel 2
Channel 3
(Continued)
15.0
15.5
16.0
17.0
18.0
46.0
47.0
48.0
50.0
52.0
72.0
74.0
76.0
0.0
0.5
1.0
1.5
: :
: :
: :
: :
8
new data. The data is then decoded and the appropriate
switch is activated to set the desired attenuation level for the
selected channel. This process is continued each and every
time an attenuation change is made. Each channel is up-
dated, only, when that channel is selected for an attenuator
change or the system is powered down and then back up
again. When the µPot is powered up, each channel is placed
into the muted mode.
µPot LADDER ARCHITECTURE
Each channel of a µPot has its own independent resistor
ladder network. As shown in Figure 8, the ladder consists of
multiple R1/R2 elements which make up the attenuation
scheme. Within each element there are tap switches that
select the appropriate attenuation level corresponding to the
data bits in Table 1. It can be seen in Figure 8 that the input
impedance for the channel is a constant value regardless of
which tap switch is selected, while the output impedance
varies according to the tap switch selected.
DIGITAL LINE COMPATIBILITY
The µPot’s digital interface section is compatible with either
TTL or CMOS logic due to the shift register inputs acting
upon a threshold voltage of 2 diode drops or approximately
1.4V.
DIGITAL DATA-OUT PIN
The DATA-OUT pin is available for daisy-chain system con-
figurations where multiple µPots will be used. The use of the
daisy-chain configuration allows the system designer to use
only one DATA and one LOAD/SHIFT line per chain, thus
simplifying PCB trace layouts.
In order to provide the highest level of channel separation
and isolate any of the signal lines from digital noise, the
DATA-OUT pin should be terminated through a 2 kΩ resistor
if not used. The pin may be left floating, however, any signal
noise on that line may couple to adjacent lines creating
higher noise specs.
FIGURE 8. µPot Ladder Architecture
01195811