CS8427-CSZ Cirrus Logic Inc, CS8427-CSZ Datasheet - Page 31

• Manufacturer Part Number: CS8427-CSZ
• Description: IC TXRX DGTL AUDIO 96KHZ 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Transceiver (DIX)r

Specifications of CS8427-CSZ

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Audio Control Type: Digital
• Control Interface: I2C, Serial
• Control / Process Application: AV & DVD Receivers, CD-R, Digital Mixing Consoles
• Supply Voltage Range: 2.85V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1783 - EVALUATION BOARD FOR CS8427
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1733

11.5 Serial Audio Input Port Data Format (05h)
SIMS - Master/Slave Mode Selector
SISF - ISCLK frequency (for master mode)
SIRES1:0 - Resolution of the input data, for right-justified formats
SIJUST - Justification of SDIN data relative to ILRCK
SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats
SISPOL - ISCLK clock polarity
SILRPOL - ILRCK clock polarity
11.6 Serial Audio Output Port Data Format (06h)
SOMS - Master/Slave Mode Selector
SOSF - OSCLK frequency (for master mode)
DS477F5
SOMS
SIMS
7
7
Default = ‘0’
0 - Serial audio input port is in slave mode
1 - Serial audio input port is in master mode
Default = ‘0’
0 - 64 * Fsi
1 - 128 * Fsi
Default = ‘00’
00 - 24 bit resolution
01 - 20 bit resolution
10 - 16 bit resolution
11 - Reserved
Default = ‘0’
0 - Left-justified
1 - Right-justified
Default = ‘0’
0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge
1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge
Default = ‘0’
0 - SDIN sampled on rising edges of ISCLK
1 - SDIN sampled on falling edges of ISCLK
Default = ‘0’
0 - SDIN data is for the left channel when ILRCK is high
1 - SDIN data is for the right channel when ILRCK is high
Default = ‘0’
0 - Serial audio output port is in slave mode
1 - Serial audio output port is in master mode
Default = ‘0’
0 - 64 * Fso
1 - 128 * Fso
SOSF
SISF
6
6
SORES1
SIRES1
5
5
SORES0
SIRES0
4
4
SOJUST
SIJUST
3
3
SODEL
SIDEL
2
2
SOSPOL
SISPOL
1
1
CS8427
SOLRPOL
SILRPOL
0
0
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