CS44800-CQZR Cirrus Logic Inc, CS44800-CQZR Datasheet - Page 70

• Manufacturer Part Number: CS44800-CQZR
• Description: IC AMP CTLR DGTL 8CH 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Amplifierr

Specifications of CS44800-CQZR

• Package / Case: 64-LQFP
• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Product: Class-D
• Operating Supply Voltage: 2.5 V
• Supply Current: 150 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Supply Type: Digital
• Supply Voltage (max): 2.62 V
• Supply Voltage (min): 2.37 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1532 - BOARD EVAL FOR CS44800 PWM CTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

70
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0])
7.31
7.31.1 Differential Signal Delay (DIFF_DLY[2:0])
7.31.2
DIFF_DLY2
7
PWMOUT Delay Register (address 33h)
state by setting the PDN bit in the register
page 51
Default = 00000
Function:
The PWM Minimum Pulse registers allow settings for the minimum allowable pulse width on each of the
PWMOUT differential signal pairs, PWMOUTxx+ and PWMOUTxx-. The value selected in this register is
applicable to all PWM channels. The effective minimum pulse is calculated by multiplying the register val-
ue by the period of the PWM_MCLK. This parameter can only be changed when all modulators and as-
sociated logic are in the power-down state by setting the PDN bit in the register
Power Control (address 02h)” on page 51
will be ignored.
Default = 000
Function:
The Differential Signal Delay bits allow delay adjustment between each channel’s differential signals,
PWMOUTxx+ and PWMOUTxx-. This set of bits control the delay between PWMOUTxx+ and PW-
MOUTxx- across all active channels. The value of this register determines the amount of delay inserted
in the output path. The effective delay is calculated by multiplying the register value by the period of the
PWM_MCLK. This parameter can only be changed when all modulators and associated logic are in the
power-down state by setting the PDN bit in the register
02h)” on page 51
Default = 00000
Function:
Channel Delay Settings (CHNL_DLY[4:0])
DIFF_DLY1
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
6
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
DIFF_DLY0
Table 14. PWM Minimum Pulse Width Settings
5
Table 15. Differential Signal Delay Settings
MIN_PULSE[4:0]
Binary Code
Binary Code
000
001
100
00000
10100
111
00110
11111
CHNL_DLY4
4
to a 1b. Attempts to write this register while the PDN is not set
“Clock Configuration and Power Control (address 02h)” on
Delay Setting (multiply by
PWM_MCLK period)
PWM_MCLK period)
Setting (multiply by
CHNL_DLY3
Minimum Pulse
0 - no minimum
0 - no delay
3
“Clock Configuration and Power Control (address
20
31
6
1
4
7
CHNL_DLY2
2
CHNL_DLY1
“Clock Configuration and
1
CS44800
CHNL_DLY0
DS632F1
0