ADM6822 Analog Devices, ADM6822 Datasheet - Page 9

• Manufacturer Part Number: ADM6822
• Description: Low Voltage Supervisory Circuit with Watchdog, Manual Reset and Active-Low, Open-Drain Reset Output
• Manufacturer: Analog Devices

Specifications of ADM6822

• Batt-backup-flg: No
• Manual Reset Capability: Yes
• Package: SOT
• Power Fail Indicator: No
• Reset Threshold Summary: 9 Options--1.58 to 4.63V
• Reset Output-stage: Active-Low/Open-Drain
• Min Reset Timeout (ms): 140
• Typ Watchdog Timeout (ms): 1600
• Watchdog Timer: Yes

CIRCUIT DESCRIPTION
The ADM682x provide microprocessor supply voltage
supervision by controlling the microprocessor’s reset input.
Code execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold. In addition, the
ADM682x allow supply voltage stabilization with a fixed
timeout before the reset deasserts after the supply voltage rises
above the threshold.
Problems with microprocessor code execution can be
monitored and corrected with a watchdog timer (ADM6821/
ADM6822/ADM6823/ADM6824). When watchdog strobe
instructions are included in microprocessor code, a watchdog
timer detects if the microprocessor code breaks down or
becomes stuck in an infinite loop. If this happens, the watchdog
timer asserts a reset pulse, which restarts the microprocessor in
a known state.
If the user detects a problem with the system’s operation,
a manual reset input is available (ADM6821/ADM6822/
ADM6823/ADM6825) to reset the microprocessor by means
of an external push-button, for example.
RESET OUTPUT
The ADM6821 features an active-high push-pull reset output.
The ADM6822 features an active-low open-drain reset output,
while the ADM6823 features an active-low push-pull output.
The ADM6824/ADM6825 feature dual active-low and active-
high push-pull reset outputs. For active-low and active-high
outputs, the reset signal is guaranteed to be logic low and logic
high, respectively, for V
The reset output is asserted when V
threshold (V
serviced within the watchdog timeout period (t
remains asserted for the duration of the reset active timeout
period (t
transitions from low to high, or after the watchdog timer times
out. Figure 14 shows the reset outputs.
RESET
RESET
V
CC
RP
V
V
V
) after V
1V
1V
0V
0V
0V
CC
CC
CC
TH
), when MR is driven low, or when WDI is not
Figure 14. Reset Timing Diagram
CC
V
rises above the reset threshold, after MR
TH
CC
t
t
RP
RP
down to 1 V.
CC
is below the reset
t
RD
WD
V
TH
). Reset
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
t
RD
Rev. 0 | Page 9 of 12
MANUAL RESET INPUT
The ADM6821/ADM6822/ADM6823/ADM6825 feature a
manual reset input ( MR ), which, when driven low, asserts the
reset output. When MR transitions from low to high, reset
remains asserted for the duration of the reset active timeout
period before deasserting. The MR input has a 50 kΩ internal
pull-up so that the input is always high when unconnected. An
external push-button switch can be connected between MR and
ground so that the user can generate a reset. Debounce circuitry
is integrated on-chip for this purpose. Noise immunity is
provided on the MR input, and fast, negative-going transients of
up to 100 ns (typ) are ignored. A 0.1 μF capacitor between MR
and ground provides additional noise immunity.
WATCHDOG INPUT
The ADM6821/ADM6822/ADM6823/ADM6824 feature a
watchdog timer, which monitors microprocessor activity. A
timer circuit is cleared with every low-to-high or high-to-low
logic transition on the watchdog input pin (WDI), which
detects pulses as short as 50 ns. If the timer counts through the
preset watchdog timeout period (t
microprocessor is required to toggle the WDI pin to avoid
being reset. Failure of the microprocessor to toggle WDI within
the timeout period therefore indicates a code execution error,
and the reset pulse generated restarts the microprocessor in a
known state.
In addition to logic transitions on WDI, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condi-
tion on V
watchdog timer is cleared and does not begin counting again
until reset deassserts. The watchdog timer can be disabled by
leaving WDI floating or by three-stating the WDI driver.
RESET
WDI
V
CC
CC
V
V
V
1V
0V
0V
0V
CC
CC
CC
or MR being pulled low. When reset is asserted, the
Figure 15. Watchdog Timing Diagram
V
t
RP
TH
WD
), reset is asserted. The
t
WD
t
RD