ADM698 Analog Devices, ADM698 Datasheet - Page 4

• Manufacturer Part Number: ADM698
• Description: Microprocessor Supervisory Circuit
• Manufacturer: Analog Devices

Specifications of ADM698

• # Of Monitored Voltages: 1
• Backup-battery Switch: No
• Manual Reset Capability: No
• Package: DIP,SOIC
• Reset Threshold Summary: 4.65V
• Reset Output-stage: Active-High/Push-Pull,Active-Low/Push-Pull
• Min Reset Timeout (ms): 140
• Watchdog Timer: No

ADM698/ADM699
CIRCUIT INFORMATION
Power Fail RESET
A precision voltage detector monitors V
RESET output to hold the microprocessor’s Reset line low when
V
reset voltage threshold is set to accommodate a 5% variation on
V
glitches on V
On power up, an internal monostable holds RESET low for
140 ms after V
power supply to stabilize on power up and also prevents re-
peated toggling of RESET even if the 5 V power drops out and
recovers with each power line cycle. In order to prevent
mistriggering due to transient voltage spikes, it is recommended
that a 0.1 F capacitor be connected at the V
The RESET output is guaranteed to remain low with V
low as 1 V. This holds the microprocessor in a stable shutdown
condition as the power supply comes up.
On the 16-lead SOIC package, an active high RESET output is
also provided. This is the complement of RESET and is in-
tended for microprocessors requiring an active high signal.
CC
CC
RESET
Figure 4. Watchdog Timeout Period vs. Temperature
. The voltage detector has 40 mV hysteresis to ensure that
V
falls below the reset threshold (4.65 V) (see Figure 4). The
CC
CC
CC
V
do not activate the RESET output.
2
8-Pin Plastic DIP
rises above the reset threshold. This allows the
t
V
V
t
1
1
1
2
= RESET TIME
= RESET VOLTAGE THRESHOLD
= RESET VOLTAGE THRESHOLD +
THRESHOLD HYSTERESIS
(N-8)
V
1
V
CC
2
t
and generates a
1
CC
pin.
Dimensions shown in inches and (mm).
0.022 (0.558)
0.014 (0.356)
OUTLINE DIMENSIONS
SEATING
PLANE
CC
PIN 1
0.200
(5.08)
MAX
as
8-Pin Cerdip
V
1
8
1
0.015 (0.381)
0.008 (0.204)
0.420 (10.67)
0.100 (2.54)
0.320 (8.13)
0.290 (7.37)
(Q-8)
–4–
BSC
MAX
Watchdog Timer (ADM699 Only)
The watchdog timer input (WDI) monitors an I/O line from the
onds to verify correct software execution. Failure to toggle the
line indicates that the P system is not correctly executing its
program and may be tied up in an endless loop. If this happens,
a reset pulse is generated to initialize the processor.
The WDI input is a three level input and will recognize a low
to- high or a high-to-low transition on its input. The watchdog
timer is reset by each WDI transition and then begins its
timeout period. If the WDI pin remains either high or low, reset
pulses will be issued every 1.6 seconds typically. If the watch-
dog timer is not needed, the WDI input should be left floating.
The Watchdog Output (WDO) (SOIC package Only) provides
watchdog status information. It is driven low if WDI is not
toggled within the watchdog timeout period. It goes high at the
next WDI transition. It is also set high when V
reset threshold.
Figure 5. Watchdog Timeout Period and Reset Active Time
P system. The P must toggle this input once every 1.6 sec-
5
4
RESET
0.060 (1.52)
0.015 (0.38)
0.310 (7.87)
0.220 (5.59)
WDO
0.070 (1.78)
0.30 (0.76)
WDI
0.150
(3.81)
MIN
t
1
t
t
1 = RESET TIME
2 = WATCHDOG TIME OUT PERIOD
(0.32)
0.013
(7.60)
0.030
(0.75)
0.299
t
2
0.012
(0.3)
16
1
16-Lead SOIC
t
1
0.05 (1.27)
0.413 (10.50)
REF
(R-16)
t
2
0.019 (0.49)
CC
t
1
0.042
(1.07)
9
8
falls below the
(10.65)
0.104
(2.65)
0.419
REV. 0