ADP1043A Analog Devices, ADP1043A Datasheet - Page 35

• Manufacturer Part Number: ADP1043A
• Description: Digital Controller for Isolated Power Supply Applications
• Manufacturer: Analog Devices

DETAILED REGISTER DESCRIPTIONS
FAULT REGISTERS
Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared
only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also
note that these register bits are cleared when read via the I
fault register be read again after the faults disappear to ensure that the register is reset.
Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Table 10. Register 0x02—Fault Register 3 and Register 0x06—Latched Fault Register 3 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Name
Power supply
OrFET
PGOOD1 fault
PGOOD2 fault
SR off
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
Name
Voltage
continuity
UVP
Accurate OrFET
disable
VDD UV
VCORE OV
VDD OV
Load OVP
Local OVP
Name
OTP
Reserved
Share bus
Constant current
Reserved
Line impedance
Soft start filter
External flag
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
Description
1 = power supply is off. All PWM outputs are disabled. This bit
stays high until the power supply is restarted.
1 = OrFET control signal at the GATE pin (Pin 16) is off.
1 = Power-Good 1 fault. At least one of the following flags has been
set: power supply, CS1 fast OCP, CS1 accurate OCP, CS2 accurate
OCP, UVP, local OVP, or load OVP.
1 = Power-Good 2 fault. At least one of the following flags has
been set: power supply, OrFET, CS1 fast OCP, CS1 accurate OCP,
CS2 accurate OCP, voltage continuity, UVP, accurate OrFET disable,
ACSNS, external flag (FLAGIN), VCORE OV, VDD OV, local OVP, load
OVP, OTP, CRC fault, and EEPROM unlocked. (The user can choose to
ignore one or more flags. See Table 41 for more information.)
Sync rects are disabled. This flag is set when one of the following
cases is true:
SR1 and SR2 are disabled by the user.
The load current has fallen below the threshold in Register 0x3B.
A flag that was configured to disable the sync rects has been set.
CS1 current is above its fast overcurrent protection limit. This is a
1.2 V threshold on the CS1 pin. Fast OCP is a comparator.
CS1 current is above its accurate overcurrent protection limit.
CS2 current is above its accurate overcurrent protection limit.
2.5 V VCORE is above limit.
VS2 or VS3 is above its overvoltage limit.
Description
Voltage differential between VS1 and VS2 pins or between VS2
and VS3 pins is outside limits. Either (VS1 − VS2) > 100 mV or
(VS2 − VS3) > 100 mV.
VS1 is below its undervoltage limit.
Reverse voltage across CS2 pins is above limit. This is the accurate
OrFET reverse voltage.
VDD is below limit.
VDD is above limit. The I
toggle is required to restart the power supply.
VS1 is above its overvoltage limit.
Description
Temperature is above OTP limit.
Reserved.
Current share is outside regulation limit.
Power supply is operating in constant current mode (constant
current mode is enabled).
Reserved.
Line impedance between VS2 and VS3 is above limit.
The soft start filter is in use.
The external flag pin (FLAGIN) is set.
2
C interface unless the fault is still present. It is recommended that the latched
2
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C interface stays functional, but a PSON
Register
0x30
0x2D
0x5D
0x3B
0x08 to 0x0D
0x22
0x26
Register
0x34
0x30
0x0E
0x33
0x32
Register
0x2F
0x2A
0x27
0x35
0x5F
Action
Programmable
Programmable
Programmable
Immediate shutdown
Immediate shutdown
Programmable
Programmable
Programmable
Action
Programmable
Programmable
None
None
None
Programmable
Action
None
None
None
None
Programmable
Programmable
Programmable
ADP1043A