ADP1879 Analog Devices, ADP1879 Datasheet - Page 17

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ADP1879

Manufacturer Part Number
ADP1879
Description
Synchronous Buck Controller with Constant On-Time and Valley Current Mode with Power Saving Mode
Manufacturer
Analog Devices
Datasheet
Data Sheet
THEORY OF OPERATION
BLOCK DIAGRAM
The
step-down controllers that provide superior transient response,
optimal stability, and current-limit protection by using a constant
on time, pseudo fixed frequency with a programmable current
sense gain, current control scheme. In addition, these devices offer
ADP1878/ADP1879
COMP
VREG
EN
SS
FB
630mV
I
are versatile current-mode, synchronous
SS
0.6V
REF_ZERO
ERROR
AMP
PRECISION
ENABLE
LOWER
CLAMP
COMP
SS_REF
THRESHOLD/
ADP1878/ADP1879
HYSTERESIS
REF_ZERO
SS
COMP
LDO
AND REFERENCE
BIAS BLOCK
AMP
CS
REF
PWM
Figure 64.
PSM
GND
TO ENABLE
ALL BLOCKS
CS GAIN SET
IREV
COMP
ADP1878/ADP1879
Rev. 0 | Page 17 of 40
INFORMATION
t
TON
BG_REF
IN_PSM
IN_SS
IN_HICCUP
COMP
PWM
IREV
ON
ADC
MACHINE
RES
TIMER
optimum performance at low duty cycles by using a valley, current-
mode control architecture. This allows the
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.
STATE
VREG
Block Diagram
HS_0
SW
LS_0
RES DETECT AND
GAIN SET
SW
HS
LS
690mV
530mV
600mV
FB
C
VREG
I
0.4V
LEVEL
R (TRIMMED)
SHIFT
SW FILTER
t
ON
= 2RC(V
HS
LS
OUT
VREG
/V
IN
)
300kΩ
ADP1878/ADP1879
800kΩ
8kΩ
ADP1878/ADP1879
PGOOD
VIN
BST
DRVH
SW
DRVL
PGND

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