ADP1864 Analog Devices, ADP1864 Datasheet - Page 12

• Manufacturer Part Number: ADP1864
• Description: Constant Frequency Current-Mode Step-Down DC-to-DC Controller in TSOT
• Manufacturer: Analog Devices

ADP1864
LAYOUT CONSIDERATIONS
Layout is important with all switching regulators, but is particu-
larly important for high switching frequencies. Ensure all high
current paths are as wide as possible to minimize track induc-
tance, which causes spiking and electromagnetic interference
(EMI). These paths are shown in bold in Figure 15. Place the
current sense resistor and the input capacitor(s) as close to the
IN pin as possible.
Keep the PGND connections for the diode, input capacitor(s),
and output capacitor(s) as close together as possible on a wide
PGND plane. Connect the PGND and GND planes at a single
point with a narrow trace close to the ADP1864 GND connection.
Ensure the feedback resistors are placed as close as possible
to the FB pin to prevent stray pickup. To prevent extra noise
pickup on the FB line, do not allow the feedback trace from
the output voltage to FB to pass right beside the drain of the
external PFET. Add an extra copper plane at the connection of
the FET drain and the cathode of the diode to help dissipate the
heat generated by losses in those components.
All analog components are grouped together on the left side
of the evaluation board (left side of the ADP1864 DUT, see
Figure 16), including compensation and FB components. All
power components are located on the right side of the board
(MOSFET, inductor, input bypass capacitors, output capacitors,
and power diode).
All noisy nodes (P-channel drain, power diode cathode, and
inductor terminal) are located along the bottom portion of the
evaluation board on the top layer (see Figure 16). A substantial
amount of copper has been allocated for this area with ample
track spacing to minimize coupling (crosstalk) effects during
switching.
The FB tap is isolated and runs from the R
right portion of the board on the bottom layer (see Figure 17)
to minimize EMI pickups emitted from the power components
along the bottom portion of the evaluation board’s top layer (see
Figure 16). Sufficient track spacing is placed from the main
power ground plane located near the center of the board to
effectively decouple this track.
There are two ground planes on the top layer: the analog
ground plane is on the left and the power ground plane on
the right. An analog ground pickup point projects down to
the bottom layer and through a single narrow and isolated
track (see Figure 17).
The P-channel gate should have an isolated trace (bottom layer)
tying back to Pin 6 of the DUT by via connections.
TOP
, along the upper
Rev. B | Page 12 of 16
R
Figure 17. Bottom Layer of an Example Layout of an ADP1864 Application
BOTTOM
C2
Figure 16. Top Layer of an Example Layout for an ADP1864 Application
1
2
3
C2
POWER COMPONENTS TO MINIMIZE EMI PICKUP.
THIS CONNECTION AWAY FROM THE CATHODE OF D1 AND DRAIN OF
PFET IS TO ENSURE THAT NOISE DOES NOT COUPLE INTO THIS TRACK.
MINIMIZE STRAY PARASITIC EFFECTS TOWARDS THE ANALOG
COMPONENTS (FB AND COMPENSATION COMPONENTS).
FB TAP FROM OUTPUT TO R
ISOLATED TRACE FOR GATE CONNECTION OF THE PFET. ROUTING OF
ISOLATED TRACK FOR CONNECTING AGND TO PGND. THIS HELPS
Figure 15. Application Circuit Showing High Current Paths (in Bold)
R
TOP
R2
R2
C1
R
TOP
FB TAP
R
1
BOTTOM
GROUND TAP
C1
3
1
2
3
ANALOG
2
COMP
FB
GND
R
S
ISOLATED POWER GROUND PLANE. USE A SUBSTANTIAL
AMOUNT OF COPPER TO BEST ACCOMMODATE
THIS HIGH CURRENT PATH. ALSO PROVIDES AID
FOR POWER DISSIPATION.
ADP1864
U1
CE1
PGATE
NOISY POWER PLANE IS LOCATED ON THIS
SIDE OF THE BOARD TO ACCOMODATE SPIKY
NODES AND MINIMIZE EMI EFFECTS TO THE
REST OF THE SYSTEM.
TOP
. TRACE SHOULD BE AWAY FROM
CS
IN
4
6
5
R
D1
S
U1
CE2
D1
CE1
L1
L1
CE2
V
OUT
V
PGND
V
IN
OUT