ADP151 Analog Devices, ADP151 Datasheet - Page 14

• Manufacturer Part Number: ADP151
• Description: Ultra Low Noise, 200 mA CMOS Linear Regulator
• Manufacturer: Analog Devices

ADP151
Figure 34 through Figure 38 show the typical performance of the
4 V LDO circuit.
The noise performance of the 4 V LDO circuit is only about 1 μV
worse than the same LDO used at 3.3 V because the output noise of
the circuit is almost solely determined by the LDO and not the
external components. The small difference may be attributed to the
internally generated noise in the LDO ground current working with
R2. By keeping R2 small, this noise contribution can be minimized.
The PSRR of the 4 V circuit is as much as 10 dB poorer than the
3.3 V LDO with 500 mV of headroom because the ground current
of the LDO varies slightly with input voltage. This, in turn,
modulates V
increasing the headroom to 1 V, the PSRR performance is
nearly restored to the performance of the fixed output LDO.
Figure 34. 4 V LDO Circuit, Typical Load Regulation over Temperature
Figure 35. 4 V LDO Circuit, Typical Line Regulation over Load Current
4.040
4.035
4.030
4.025
4.020
4.015
4.010
4.005
4.000
4.04
4.03
4.02
4.01
4.00
3.99
3.98
3.97
3.96
4.4
OFFSET
–40
LOAD = 10mA
LOAD = 20mA
LOAD = 50mA
LOAD = 100mA
LOAD = 150mA
LOAD = 200mA
LOAD = 10mA
LOAD = 20mA
LOAD = 50mA
LOAD = 100mA
LOAD = 150mA
LOAD = 200mA
and reduces the PSRR of the regulator. By
4.6
JUNCTION TEMPERATURE (°C)
–5
4.8
V
IN
25
(V)
5.0
85
5.2
125
5.4
Rev. D | Page 14 of 24
Figure 38. 4 V LDO Circuit, Typical PSRR vs. Load Current, 500 mV Headroom
Figure 37. 4 V LDO Circuit, Typical PSRR vs. Load Current, 1 V Headroom
Figure 36. 4 V LDO Circuit, Typical RMS Output Noise, 10 Hz to 100 kHz
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
11
10
9
8
0
0
1
10
10
200mA
100mA
50mA
10mA
200mA
100mA
50mA
10mA
100
100
10
LOAD CURRENT (mA)
1k
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
10k
100
100k
100k
1M
1M
1k
10M
10M