ADUC812 Analog Devices, ADUC812 Datasheet - Page 22

• Manufacturer Part Number: ADUC812
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC812

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 8

ADuC812
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is illustrated in Figure 18. Details of the actual DAC
architecture can be found in U.S. Patent Number 5969657
(www.uspto.gov). Features of this architecture include inherent
guaranteed monotonicity and excellent differential linearity.
As illustrated in Figure 18, the reference source for each DAC is
user selectable in software. It can be either AV
0-to-AV
0 V to the voltage at the AV
DAC output transfer function spans from 0 V to the internal
V
V
rail output stage implementation. This means that unloaded, each
output is capable of swinging to within less than 100 mV of both
AV
(when driving a 10 kΩ resistive load to ground) is guaranteed
through the full transfer function except codes 0 to 48, and, in
0-to-AV
near ground and V
amplifier, and a general representation of its effects (neglecting
offset and gain error) is illustrated in Figure 19. The dotted line
in Figure 19 indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output amplifier. Note
that Figure 19 represents a transfer function in 0-to-V
only. In 0-to-V
would be similar, but the upper portion of the transfer function
would follow the “ideal” line right to the end (V
not V
REF,
REF
Figure 18. Resistor String DAC Functional Equivalent
DD
pin. The DAC output buffer amplifier features a true rail-to-
DD
or if an external reference is applied, the voltage at the
and ground. Moreover, the DAC’s linearity specification
DD
DD
), showing no signs of endpoint linearity errors.
mode only, codes 3995 to 4095. Linearity degradation
mode, the DAC output transfer function spans from
REF
AV
V
REF
DD
mode (with V
DD
is caused by saturation of the output
R
R
R
R
R
DD
REF
pin. In 0-to-V
< V
ADuC812
(FROM MCU)
DISABLE
OUTPUT
BUFFER
HIGH-Z
DD
) the lower nonlinearity
REF
8
REF
DD
mode, the
or V
in this case,
DD
REF.
mode
In
–22–
The endpoint nonlinearities conceptually illustrated in Figure 19
get worse as a function of output loading. Most of the ADuC812’s
data sheet specifications assume a 10 kΩ resistive load to ground
at the DAC output. As the output is forced to source or sink
more current, the nonlinear regions at the top or bottom
(respectively) of Figure 19 become larger. With larger current
demands, this can significantly limit output voltage swing.
Figure 20 and Figure 21 illustrate this behavior. It should be noted
that the upper trace in each of these figures is only valid for an
output range selection of 0-to-AV
loading will not cause high-side voltage drops as long as the
reference voltage remains below the upper trace in the correspond-
ing figure. For example, if AV
high-side voltage will not be affected by loads less than 5 mA.
But somewhere around 7 mA the upper curve in Figure 21 drops
below 2.5 V (V
output will not be capable of reaching V
V
V
DD
Figure 20. Source and Sink Current Capability with
V
DD
Figure 19. Endpoint Nonlinearities Due to Amplifier
Saturation
REF
– 100mV
– 50mV
100mV
50mV
0mV
= V
V
5
4
3
2
1
0
DD
000 HEX
0
DD
DAC LOADED WITH 0FFF HEX
DAC LOADED WITH 0000 HEX
= 5 V
REF
), indicating that at these higher currents the
SOURCE/SINK CURRENT – mA
5
DD
DD
= 3 V and V
. In 0-to-V
REF
10
.
REF
REF
= 2.5 V, the
mode, DAC
FFF HEX
15
REV. E