ADP8861 Analog Devices, ADP8861 Datasheet - Page 4

• Manufacturer Part Number: ADP8861
• Description: Charge Pump, 7-Channel Smart LED Driver with I2C Interface
• Manufacturer: Analog Devices

Specifications of ADP8861

• Vin Range: 2.5 to 5.5V
• Vout (v): 4.3 to 5.5
• Synchronous: No
• Package: 20-Lead LFCSP,20-Lead WLCSP
• Led Configuration: Parallel
• Topology: Capacitive
• I2c Support: Yes
• Max Iout (ma): 60mA
• Brightness Control: PWM
• Peak Efficiency (%): 89%
• Switching Frequency: 1.32MHz
• Over Volt Protection (v): 5.8V

ADP8861
Parameter
FAULT PROTECTION
I
I
1
2
3
I
2
2
2
Current source matching is calculated by dividing the difference between the maximum and minimum currents from the sum of the maximum and minimum.
V
V
C INTERFACE
C TIMING SPECIFICATIONS
C TIMING DIAGRAM
IL
IH
Start-Up Charging Current Source
Output Voltage Threshold
Output Overvoltage Protection
Thermal Shutdown
Isolation from Input to Output
Time to Validate a Fault
Operating V
Logic Low Input
Logic High Input
Delay from Reset Deassertion to
SCL Frequency
SCL High Time
SCL Low Time
Setup Time
Hold Time
Bus Free Time (Stop and Start
Rise Time (SCL and SDA)
Fall Time (SCL and SDA)
Pulse Width of Suppressed Spike
Capacitive Load per Bus Line
is a function of the input voltage. See Figure 16 in the Typical Performance Characteristics section for typical values over operating ranges.
is a function of the input voltage. See Figure 16 in the Typical Performance Characteristics section for typical values over operating ranges.
Exit Soft Start
Short-Circuit Protection
Activation Level
OVP Recovery Hysteresis
Threshold
Hysteresis
During Fault
I
Data
Repeated Start
Stop Condition
Data
Start/Repeated Start
Conditions)
2
C Access
SDA
SCL
DDIO
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Voltage
2
3
S
t
LOW
Symbol
I
V
V
V
V
TSD
TSD
I
t
V
V
V
t
f
t
t
t
t
t
t
t
t
t
t
t
C
SS
OUTLKG
SCL
FAULT
RESET
HIGH
LOW
SU, DAT
SU, STA
SU, STO
HD, DAT
HD, STA
BUF
R
F
SP
t
OUT
OUT(START)
OUT(SC)
OVP
DDIO
IL
IH
B
R
t
HD, DAT
(HYS)
t
SU, DAT
Test Conditions/Comments
V
V
V
V
V
V
Guaranteed by design
IN
OUT
OUT
IN
IN
IN
Figure 2. I
= 3.6 V, V
= 5.5 V, V
= 2.5 V
= 5.5 V
rising
falling
t
HIGH
Rev. A | Page 4 of 40
2
C Interface Timing Diagram
OUT
OUT
t
t
F
= 0.8 × V
= 0 V, Bit nSTBY = 0
SU, STA
t
F
IN
Sr
t
HD, STA
t
SP
t
SU, STO
Min
2.5
1.3
100
0.6
0.6
0
1.3
20 + 0.1 C
0
1.55
0.6
0.6
20 + 0.1 C
t
R
B
B
P
t
BUF
Typ
3.75
0.92 × V
0.55 × V
5.8
500
150
20
2
S
IN
IN
Max
5.5
1.5
5.5
0.5
20
400
0.9
300
300
50
400
Unit
mA
V
V
V
mV
°C
°C
μA
μs
V
V
V
μs
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
ns
ns
pF