ADP5520 Analog Devices, ADP5520 Datasheet - Page 15

• Manufacturer Part Number: ADP5520
• Description: Backlight Driver with I/O Expander
• Manufacturer: Analog Devices

Specifications of ADP5520

• Vin Range: 2.7 to 5.5V
• Vout (v): 24 to 27
• Synchronous: No
• Package: 24-Lead LFCSP
• Led Configuration: Serial
• Topology: Inductive
• I2c Support: Yes
• Max Iout (ma): 30mA
• Brightness Control: I2C
• Switching Frequency: 1MHz
• Over Volt Protection (v): 24V

takes 80 ms (typical). Filter times of between 80 ms and 10 sec
can be programmed for the comparators before they change state.
It is also possible to use the light sensor comparators in a single
shot mode. After the single shot measurement is completed, the
internal state machine clears the FORCE_RD bit.
The interrupt flag, CMPR_INT, is set in Register 0x00 if either
of the L2_OUT or L3_OUT status bits change state, meaning
interrupts can be generated if ambient light conditions transition
between any of the programmed trip points. CMPR_INT can
cause the nINT pin to be asserted if the CMPR_IEN bit is set in
Register 0x00. The CMPR_INT flag can be cleared only by
writing a 1 to it.
AUTOMATIC BACKLIGHT ADJUSTMENT
The ambient light sensor comparators can be used to automati-
cally transition the backlight between one of its three operating
levels. To enable this mode, the BL_AUTO_ADJ bit is set in
Register 0x02.
Once enabled, the internal state machine takes control of the
BL_LVL bits and changes them based on the L2_OUT and
L3_OUT status bits. The L2_OUT status bit indicates that ambient
light conditions have dropped below the L2_TRIP point and the
backlight should be moved to its office (L2) level. The L3_OUT
status bit indicates that ambient light conditions have dropped
below the L3_TRIP point and the backlight should be moved
to its dark (L3) level. Table 6 shows the relationship between
backlight operation and the ambient light sensor comparator
outputs.
The L3_OUT status bit has greater priority, so the backlight
operates at L3 (dark) even if L2_OUT is set.
Table 6. Comparator Output Truth Table (X = Don’t Care)
BL_AUTO_ADJ
0
1
1
1
1
I/O EXPANSION PINS (GPIOs)
The eight I/O expansion pins (R0, R1, R2, R3, C0, C1, C2, and
C3) can be configured as general-purpose digital inputs, digital
inputs with pull-up, or digital outputs. Two of the I/O pins (R3
and C3) are LED current sinks by default. To use them as GPIOs,
set Bit 4 and Bit 5 in Register 0x11. Register 0x17 to Register 0x1F
are used to configure the I/O pins in GPIO mode. Figure 33
shows the typical makeup of a GPIO block, where Rx/Cx
represents any one of the eight I/O lines.
L3_OUT
X
0
0
1
1
L2_OUT
X
0
1
0
1
Backlight Operation
BL_LVL can be manually
set by the user
BL_LVL = 00, backlight
operates at L1 (daylight)
BL_LVL = 01, backlight
operates at L2 (office)
BL_LVL = 10, backlight
operates at L3 (dark)
BL_LVL = 10, backlight
operates at L3 (dark)
Rev. A | Page 15 of 40
When configured as an output, a digital buffer drives the GPIO
Rx and Cx pins to 0 V for a Logic 0 and to the VDDIO rail for a
Logic 1. Output data for each I/O is set using Register 0x1A.
Each I/O has a pull-up resistor that can be enabled when used
as an input. This can be useful for interfacing to an external
signal that has only pull-down capabilities. Pull-ups can be
enabled and disabled using Register 0x1F.
Each I/O has a debounce circuit that effectively filters out glitches
and pulses less than 75 μs (typical) to prevent false triggering
when configured as an input. By default, debounce is enabled
but can be disabled using Register 0x1E.
I/Os configured as inputs store the digital state sensed at each
pin in Register 0x19. Interrupts can be generated by digital
inputs if enabled in Register 0x1B. The input interrupt level
can be selected using Register 0x1D. Interrupts generated are
stored in Register 0x1C. The master GPI_INT bit is set if any
interrupt bits are set in Register 0x1C, and the nINT pin is
asserted.
To deassert the nINT pin and clear the GPI_INT bit, the 0x1C
register must be cleared by reading it twice (assuming the interrupt
condition has gone away), and then a 1 must be written to the
GPI_INT bit in Register 0x00. Figure 34 shows the interrupt
generation scheme, where Dx represents any one of the eight
digital input lines.
I/O EXPANSION PINS (KEYPAD MATRIX)
The eight I/O expansion pins (R0, R1, R2, R3, C0, C1, C2, and
C3) can be configured to decode a keypad matrix, consisting of
up to 16 switches (4 × 4 matrix). See the Example Circuits
section for other possible matrix configurations.
Two of the I/O pins (R3 and C3) are LED current sinks by
default. To use them as keypad decoders, set Bit 4 and Bit 5 in
Register 0x11. The R0, R1, R2, and R3 I/O pins make up the
rows of the keypad matrix. The C0, C1, C2, and C3 I/O pins
make up the columns of the keypad matrix.
0x1D
0x1B
0x19
REG
REG
REG
Dx_IN_IEN
Dx_ILVL
Dx_IN
Dx_IN_DBNC
Dx_IN
Dx_OUT
Dx_DIR
INTERRUPT
CONDITION
DECODE
Figure 34. GPIO Interrupt generation
Figure 33. Typical GPIO Block
DEBOUNCE
Dx_PULL
VDDIO
AND
READ TWICE
Dx_IN_ISTAT
VDDIO
TO CLEAR
REG 0x1C
GPIO (Rx/Cx)
TO CLEAR
REG 0x00
WRITE 1
GPI_INT
ADP5520
nINT
DRIVE