ADM8695 Analog Devices, ADM8695 Datasheet - Page 12
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ADM8695
Manufacturer Part Number
ADM8695
Description
Manufacturer
Analog Devices
Datasheet
1.ADM8690.pdf
(24 pages)
Specifications of ADM8695
Batt-backup-flg
Yes
Product Description
µP Supervisor w/ Backup Battery Switch, Adj Reset Period, Adj Watchdog Period, 4.65V Trip Voltage
Reset Threshold (v)
4.65
Min Reset Timeout (ms)
140 (Adjustable)
Reset Output-stage
Active-High/Push-Pull,Active-Low/Push-Pull
Backup-battery Switch
Yes
Chip Enable Gating
Yes
Typ Watchdog Timeout (ms)
100,1600,adj.
Package
DIP,SOIC
Us Price 1000-4999
n/a
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ADM8690/ADM8691/ADM8695
WATCHDOG TIMER RESET
The watchdog timer circuit monitors the activity of the micro-
processor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the selected
timeout period, a RESET pulse is generated.
The nominal watchdog timeout period is preset at 1.6 sec on
the ADM8690. The
a fixed timeout period—short (100 ms) or long (1.6 sec)—or for
an adjustable timeout period. Some systems are unable to service
the watchdog timer immediately after a reset; in this case, if the
short period is selected for the ADM8691/ADM8695, the device
automatically selects the long timeout period directly after a
reset is issued. The watchdog timer is restarted at the end of a
reset, regardless of whether the reset was caused by lack of
activity on WDI or by V
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur by the end of the minimum timeout period. If WDI
remains permanently high or low, reset pulses are issued after
each long (1.6 sec) timeout period. The watchdog monitor can
be deactivated by allowing the watchdog input (WDI) to float
or by connecting it to midsupply.
On the
1.6 sec, and the reset pulse width is fixed at 50 ms. The ADM8691/
ADM8695
Figure 17, Figure 18, Figure 19, and Figure 20 show the various
oscillator configurations that can be used to adjust the reset pulse
width and watchdog timeout period.
Table 5.
OSC SEL
Low
Low
Floating or high
Floating or high
1
When the OSC SEL pin is low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with an external capacitor is f
1
1
ADM8690
ADM8691
allow these times to be adjusted, as shown in Table 5.
the watchdog timeout period is fixed at
OSC IN
External clock input
External capacitor
Low
Floating or high
ADM8691/ADM8695
and
CC
ADM8695
falling below the reset threshold.
Reset Pulse Width and Watchdog Timeout Selections
can be configured for
Normal
1024 CLKs
400 ms × C/47 pF
100 ms
1.6 sec
Watchdog Timeout Period
Rev. C | Page 12 of 24
Immediately After Reset
4096 CLKs
1.6 sec × C/47 pF
1.6 sec
1.6 sec
RESET
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects either the 1.6 sec watch-
dog timeout period or the 100 ms watchdog timeout period.
When OSC IN is connected high or left floating, the 1.6 sec
timeout period is selected; when OSC IN is connected low, the
100 ms timeout period is selected. In either case, the timeout
period is 1.6 sec immediately after a reset. This gives the micro-
processor time to reinitialize the system. If OSC IN is low, the
100 ms watchdog timeout period becomes effective after the
first transition of WDI. The software should be written such
that the input/output port driving WDI is left in its power-up
reset state until the initialization routines are completed and the
microprocessor is able to toggle WDI at the minimum watchdog
timeout period of 70 ms.
WDO
WDI
t
t
t
1
2
3
Figure 16. Watchdog Timeout Period and Reset Active Time
= RESET TIME
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
t
OSC
1
(Hz) = 184,000/C (pF).
ADM8691
512 CLKs
200 ms × C/47 pF
50 ms
50 ms
t
2
t
1
Reset Active Period
t
3
ADM8695
2048 CLKs
520 ms × C/47 pF
200 ms
200 ms
Data Sheet
t
1