ADM692A Analog Devices, ADM692A Datasheet - Page 6

• Manufacturer Part Number: ADM692A
• Manufacturer: Analog Devices

Specifications of ADM692A

• Batt-backup-flg: Yes
• Product Description: µP Supervisor w/ Battery Steering, Watchdog, Pwr Fail Warning, Active Low Reset, 250mA Iout
• Reset Threshold (v): 4.4
• Min Reset Timeout (ms): 140
• Reset Output-stage: Active-Low/Push-Pull
• Backup-battery Switch: Yes
• Chip Enable Gating: ---
• Typ Watchdog Timeout (ms): 1600
• Package: DIP,SOIC
• Us Price 1000-4999: n/a

ADM690A/ADM692A/ADM802L/M/ADM805L/M
Signal
V
RESET
RESET
PFI
PFO
WDI
Power Fail Comparator
The power fail comparator is an independent comparator
that may be used to monitor the input power supply. The
comparator’s inverting input is internally connected to a 1.25
V reference voltage. The noninverting input is available at the
PFI input. This input may be used to monitor the input power
supply via a resistive divider network. When the voltage on the
PFI input drops below 1.25 V, the comparator output (PFO)
goes low indicating a power failure. For early warning of power
failure the comparator may be used to monitor the preregulator
input simply by choosing an appropriate resistive divider
network. The PFO output can be used to interrupt the
processor so that a shutdown procedure is implemented before
the power is lost.
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is non-
inverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input as shown in
Figure 10. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise
immunity may be achieved by connecting a capacitor between
PFI and GND.
OUT
Table I. Input and Output Status in Battery Backup Mode
POWER
INPUT
Figure 9. Power Fail Comparator
R1
R2
V
PMOS switch.
Logic low.
Logic high (ADM805L, ADM805M). The open
circuit output voltage is equal to V
The power fail comparator is disabled
Logic low.
The watchdog timer is disabled
OUT
Status
POWER
INPUT
is connected to V
FAIL
1.25V
BATT
(PFO)
via an internal
POWER FAIL
OUTPUT
OUT
.
–6–
TYPICAL APPLICATIONS
Figure 11 shows a typical power monitoring, battery backup
application. V
operating conditions with V
connected to V
V
the CMOS RAM. A RESET pulse is also generated when V
falls below the reset threshold.
The watchdog timer input (WDI) monitors an I/O line from the
verify correct software execution. Failure to toggle the line
indicates that the P system is not correctly executing its
program and may be tied up in an endless loop. If this happens,
a reset pulse is generated to initialize the processor.
P system. This line must be toggled once every 1.6 seconds to
OUT
Figure 10. Adding Hysteresis to the Power Fail
Comparator
will be switched to V
UNREGULATED
BATTERY
POWER
DC
Figure 11. Typical Application Circuit
INPUT
R2
R1
OUT
R2
R1
CC
5V
PFO
0V
. If a power failure occurs, V
+
0V
powers the CMOS RAM. Under normal
+5V
V
V
L
V
PFI
H
BATT
= 1 .25 +R 1
= 1.25 1 +
V
MID
PFI
BATT
V
CC
L
GND
1.25V
V
= 1.25
CC
present, V
V
RESET
thereby maintaining power for
IN
1.25
R 2 R 3
V
R 2 +R 3
PFO
R 2
WDI
OUT
R 1 +R 2
R 2
V
–
H
V
R 1
CC
R3
R 3
– 1.25
OUT
(PFO)
CMOS RAM
POWER
µP RESET
µP NMI
I/O LINE
is internally
CC
µP SYSTEM
µP NMI
will decay and
µP POWER
TO
REV. 0
CC