AD712 Analog Devices, AD712 Datasheet - Page 11

• Manufacturer Part Number: AD712
• Description: Precision, Low Cost, High Speed, BiFET Dual Op Amp
• Manufacturer: Analog Devices

Specifications of AD712

• -3db Bandwidth: 4MHz
• Slew Rate: 20V/µs
• Vos: 300µV
• Ib: 25pA
• # Opamps Per Pkg: 2
• Input Noise (nv/rthz): 16nV/rtHz
• Vcc-vee: 9V to 36V
• Isy Per Amplifier: 2.8mA
• Packages: DIP,SOIC

SETTLING TIME
OPTIMIZING SETTLING TIME
Most bipolar high speed DACs have current outputs; therefore,
for most applications, an external op amp is required for a current-
to-voltage conversion. The settling time of the converter/op amp
combination depends on the settling time of the DAC and output
amplifier. A good approximation is
The settling time of an op amp DAC buffer varies with the noise
gain of the circuit, the DAC output capacitance, and the amount
of external compensation capacitance across the DAC output
scaling resistor.
Settling time for a bipolar DAC is typically 100 ns to 500 ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a high
speed, voltage output, digital-to-analog function. The introduction
of the AD71x family of op amps with their 1 μs (to ±0.01% of
final value) settling time permits the full high speed capabilities
of most modern DACs to be realized.
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD71x family assure 12-bit accuracy over the full
operating temperature range.
The excellent high speed performance of the AD712 is shown in
the oscilloscope photos in Figure 29 and Figure 30. Measurements
were taken using a low input capacitance amplifier connected
directly to the summing junction of the AD712, and both figures
show a worst-case situation: full-scale input transition. The 4 kΩ
[10 kΩ||8 kΩ = 4.4 kΩ] output impedance of the DAC, together
with a 10 kΩ feedback resistor, produce an op amp noise gain of
3.25. The current output from the DAC produces a 10 V step at
the op amp output (0 to −10 V shown in Figure 29, and −10 V to
0 V shown in Figure 30).
t
S
Total
=
ADJUST
(
t
S
GAIN
DAC
R2
100Ω
GND
REF
REF
) (
2
IN
+
t
0.1µF
S
–V
+
–
AMP
EE
19.95kΩ
REF
OUT
20kΩ
10V
)
2
POWER
0.1µF
GND
0.5mA
I
REF
V
CC
AD565A
Figure 31. ±10 V Voltage Output Bipolar DAC
100Ω
MSB
R1
I
I
OUT
REF
BIPOLAR
OFFSET ADJUST
DAC
= 4 ×
× CODE
Rev. H | Page 11 of 20
BIPOLAR
9.95kΩ
LSB
OFF
I
O
5kΩ
5kΩ
8kΩ
Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)
requires that 375 μV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must
be less than 375 μV. As shown in Figure 29, the total settling
time for the AD712/AD565A combination is 1.2 microseconds.
20V
SPAN
10V
SPAN
DAC
OUT
–10V
–10V
0V
0V
Figure 29. Settling Characteristics for AD712 with AD565A,
Figure 30. Settling Characteristics for AD712 with AD565A,
100
100
0%
0%
90
10
90
10
10pF
+
–
AD712
1mV
1mV
1/2
+15V
–15V
JUNCTION
Full-Scale Negative Transition
SUMMING
8
4
Full-Scale Positive Transition
OUTPUT
JUNCTION
SUMMING
0.1µF
0.1µF
5V
5V
OUTPUT
–10V TO +10V
OUTPUT
500ns
500ns
AD712