AD713 Analog Devices, AD713 Datasheet - Page 13

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AD713

Manufacturer Part Number
AD713
Description
Precision, High Speed, BiFET Quad Op Amp
Manufacturer
Analog Devices
Datasheet

Specifications of AD713

-3db Bandwidth
4MHz
Slew Rate
20V/µs
Vos
300µV
Ib
40pA
# Opamps Per Pkg
4
Input Noise (nv/rthz)
16nV/rtHz
Vcc-vee
9V to 36V
Isy Per Amplifier
3mA
Packages
DIP,SOIC

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loop gain. At high frequencies, where the loop gain is low, the
amplifier output impedance can approach its open-loop value.
ANALOG
Most IC amplifiers exhibit a minimum open-loop output imped-
ance of 25 Ω, due to current limiting resistors. A few hundred
microamps reflected from the change in converter loading can
introduce errors in instantaneous input voltage. If the analog-
to-digital conversion speed is not excessive and the bandwidth
of the amplifier is sufficient, the amplifier output returns to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidths,
yielding slow recovery from output transients. The AD713 is
ideally suited as a driver for ADCs because it offers both a wide
bandwidth and a high open-loop gain.
INPUT
±10V
1/4
AD713
100
0%
90
10
• • • •
• • • •
Figure 38. Buffer Recovery Time Source Current = 2 mA
+15V
–15V
11
4
• • • •
• • • •
0.1µF
0.1µF
1mV
Figure 37. AD713 as an ADC Buffer
• • • •
• • • •
OFFSET ADJUST
GAIN ADJUST
(Not to Scale)
• • • •
• • • •
R1 100Ω
AD574A
TOP VIEW
500mV
R2 100Ω
ANALOG COM
• • • •
• • • •
• • • •
• • • •
AD713 BUFF
10V ADC IN
10
12
13
14
11
1
2
3
4
5
6
7
8
9
V
12/8
CS
A
R/C
CE
V
AC
REF IN
V
BIP OFF
10V
20V
• • • •
• • • •
REF OUT
LOGIC
O
CC
EE
IN
IN
• • • •
• • • •
(MSB) DB11
(LSB) DB0
• • • •
• • • •
DB10
STS
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
200ns
DC
• • • •
• • • •
28
27
26
25
24
23
22
21
20
19
18
17
16
15
HIGH
BITS
MIDDLE
BITS
LOW
BITS
Rev. F | Page 13 of 20
Driving A Large Capacitive Load
The circuit of Figure 40 uses a 100 Ω isolation resistor that
enables the amplifier to drive capacitive loads exceeding
1500 pF; the resistor effectively isolates the high frequency
feedback from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low-pass filter formed by the 100 Ω series resistor and the load
capacitance, C
this connection.
R
2kΩ
10kΩ
20kΩ
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
L
100
100
0%
0%
90
10
90
10
• • • •
• • • •
• • • •
• • • •
C
1500pF
1500pF
1000pF
INPUT
Figure 40. Circuit for Driving a Large Capacitance Load
L
Figure 39. Buffer Recovery Time Sink Current = 1 mA
Figure 41. Transient Response, R
UP TO
4.99kΩ
• • • •
• • • •
• • • •
• • • •
L
. Figure 41 shows a typical transient response for
1mV
5V
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
500mV
AD713
1/4
• • • •
• • • •
• • • •
• • • •
+V
–V
11
4
S
S
• • • •
• • • •
• • • •
• • • •
0.1µF
0.1µF
AD713 BUFF
–5V ADC IN
30pF
• • • •
• • • •
• • • •
• • • •
L
= 2 kΩ, C
4.99kΩ
100Ω
• • • •
• • • •
• • • •
• • • •
1µs
L
• • • •
• • • •
• • • •
• • • •
= 500 pF
C
200ns
L
• • • •
• • • •
• • • •
• • • •
R
OUTPUT
L
AD713

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