AD813 Analog Devices, AD813 Datasheet - Page 17

• Manufacturer Part Number: AD813
• Description: Single Supply, Low Power Triple Video Amplifier
• Manufacturer: Analog Devices

Specifications of AD813

• -3db Bandwidth: 100MHz
• Slew Rate: 250V/µs
• Vos: 2mV
• Ib: 500nA
• # Opamps Per Pkg: 3
• Input Noise (nv/rthz): 3.5nV/rtHz
• Vcc-vee: 2.4V to 36V
• Isy Per Amplifier: 5.5mA
• Packages: DIP,LCC,SOIC

REV. B
Operation Using a Single Supply
The AD813 will operate with total supply voltages from 36 V
down to 2.4 V. With proper biasing (see Figure 52) it can
make an outstanding single supply video amplifier. Since the
input and output voltage ranges extend to within 1 V of the
supply rails, it will handle a 1.3 V peak-to-peak signal on a
single 3.3 V supply, or a 3 V peak-to-peak signal on a single
5 V supply. The small signal 0.1 dB bandwidths will exceed
10 MHz in either case, and the large signal bandwidths will
exceed 6 MHz.
The capacitively coupled cable driver in Figure 52 will achieve
outstanding differential gain and phase errors of 0.05% and 0.05
degrees respectively on a single 5 V supply. Resistor R2, in this
circuit, is selected to optimize the differential gain and phase by
biasing the amplifier in its most linear region.
Figure 53. Closed-Loop Gain and Phase vs. Frequency,
Circuit of Figure 52
Figure 54. Pulse Response for the Circuit of Figure 52
with +V
V
IN
30 F
1 F
C3
Figure 52. Biasing for Single Supply Operation
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
C2
0.5
0
100
S
1
90
10
0%
2 F
12.4k
C1
619
= 5 V
9k
R1
R2
500mV
500mV
1V
1k
R3
AD813
10
619
11
4
FREQUENCY – MHz
GAIN
+5V
PHASE
C
47 F
OUT
100
75
50ns
CABLE
V
G = +2
R
R
75
S
F
L
= 5V
= 619
= 150
75
1000
V
V
V
0
–90
–180
–270
OUT
IN
OUT
–17–
Disable Mode Operation
Pulling the voltage on any one of the Disable pins about 2.5 V
down from the positive supply will put the corresponding ampli-
fier into a disabled, powered down, state. In this condition, the
amplifier’s quiescent supply current drops to about 0.5 mA, its
output becomes a high impedance, and there is a high level of
isolation from input to output. In the case of the gain of two
line driver for example, the impedance at the output node will
be about the same as for a 1.4 k resistor (the feedback plus
gain resistors) in parallel with a 12.5 pF capacitor and the input
to output isolation will be about 65 dB at 1 MHz.
Leaving the Disable pin disconnected (floating) will leave the
corresponding amplifier operational, in the enabled state. The
input impedance of the disable pins is about 35 k in parallel
with a few pF. When grounded, about 50 A flows out of a
disable pin on 5 V supplies.
Input voltages greater than about 1.5 V peak-to-peak will defeat
the isolation. In addition, large signals (greater than 3 V peak-
to-peak) applied to the output node will cause the output im-
pedance to drop significantly.
When the Disable pins are driven by complementary output
CMOS logic (such as the 74HC04), the disable time is about
80 ns (until the output goes high impedance) and the enable
time is about 100 ns (to low impedance output) on 15 V sup-
plies. When operated on 15 V supplies, the disable pins
should be driven by open drain logic. In this case, pull-up resis-
tors from the disable pins to the plus supply will ensure mini-
mum switching time.
SELECT1
SELECT2
SELECT3
Figure 55. A Fast Switching 3:1 Video Mux
(Supply Bypassing Not Shown)
V
V
V
IN
IN
IN
2
3
1
75
464
75
464
75
464
13
12
10
6
5
9
590
+5V
590
590
3
4
1
2
–5V
11
14
7
8
84
84
84
CABLE
75
AD813
75
V
OUT