AD8034 Analog Devices, AD8034 Datasheet - Page 19

• Manufacturer Part Number: AD8034
• Manufacturer: Analog Devices

Specifications of AD8034

• -3db Bandwidth: 80MHz
• Slew Rate: 80V/µs
• Vos: 1mV
• Ib: 1.5pA
• # Opamps Per Pkg: 2
• Input Noise (nv/rthz): 11nV/rtHz
• Vcc-vee: 5V to 24V
• Isy Per Amplifier: 3.5mA
• Packages: SOIC,SOT

APPLICATIONS INFORMATION
HIGH SPEED PEAK DETECTOR
The low input bias current and high bandwidth of the AD8033/
AD8034 make the parts ideal for a fast settling, low leakage peak
detector. The classic fast-low leakage topology with a diode in
the output is limited to ~1.4 V p-p maximum in the case of the
AD8033/AD8034 because of the protection diodes across the
inputs, as shown in Figure 54.
Using the AD8033/AD8034, a unity gain peak detector can
be constructed that captures a 300 ns pulse while still taking
advantage of the low input bias current and wide common-
mode input range of the AD8033/AD8034, as shown in Figure 55.
~1.4V p-p MAX
Figure 54. High Speed Peak Detector with Limited Input Range
V
IN
V
IN
49.9Ω
R5
AD8033/
AD8034
1kΩ
R1
C1
39pF/
120pF
AD8034
Figure 55. High Speed, Unity Gain Peak Detector Using AD8034
1/2
–V
+V
S
S
V
OUT
Rev. D | Page 19 of 24
D1
LS4148
LS4148
10pF
D3
1kΩ
C3
R2
4.7pF
C4
Using two amplifiers, the difference between the peak and the
current input level is forced across R2 instead of either amplifier’s
input pins. In the event of a rising pulse, the first amplifier
compensates for the drop across D2 and D3, forcing the voltage
at Node 3 equal to Node 1. D1 is off and the voltage drop across
R2 is zero. Capacitor C3 speeds up the loop by providing the
charge required by the input capacitance of the first amplifier,
helping to maintain a minimal voltage drop across R2 in the
sampling mode. A negative going edge results in D2 and D3
turning off and D1 turning on, closing the loop around the
first amplifier and forcing V
the voltage across D2 zero, minimizing leakage current and
kickback from D3 from affecting the voltage across C2.
The rate of the incoming edge must be limited so that the output
of the first amplifier does not overshoot the peak value of V
before the output of the second amplifier can provide negative
feedback at the summing junction of the first amplifier. This
is accomplished with the combination of R1 and C1, which
allows the voltage at Node 1 to settle to 0.1% of V
The selection of C2 and R3 is made by considering droop
rate, settling time, and kickback. R3 prevents overshoot from
occurring at Node 3. The time constants of R1, C1 and R3, C2
are roughly equal to achieve the best performance. Slower time
constants can be selected by increasing C2 to minimize droop
rate and kickback at the cost of increased settling time. R1 and
C1 should also be increased to match, reducing the incoming
pulse’s effect on kickback.
R4
6kΩ
LS4148
D2
200Ω
C2
R3
180pF/
560pF
OUT
AD8034
1/2
− V
IN
+V
–V
across R2. R4 makes
AD8033/AD8034
S
S
V
OUT
IN
in 270 ns.
IN