AD7834 Analog Devices, AD7834 Datasheet - Page 22

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AD7834

Manufacturer Part Number
AD7834
Description
LC2MOS Quad 14-Bit DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD7834

Resolution (bits)
14bit
Dac Update Rate
100kSPS
Dac Settling Time
10µs
Max Pos Supply (v)
+15.75V
Single-supply
No
Dac Type
Voltage Out
Dac Input Format
Ser

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AD7834/AD7835
INTERFACING THE AD7835—8-BIT INTERFACE
Figure 32 shows an 8-bit interface between the AD7835 and
a generic 8-bit microcontroller/DSP processor. Pin D13 to
Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the
processor are connected to Pin D7 to Pin D0 of the AD7835.
BYSHF is driven by the A0 line of the processor. This maps the
DAC upper bits and lower bits into adjacent bytes in the proces-
sor address space. Table 14 shows the truth table for addressing
the DACs in the AD7835. For example, if the base address for the
DACs in the processor address space is decoded by the upper
address bits to location HC000, then the upper and lower bits of
the first DAC are at locations HC000 and HC001, respectively.
1
MICROCONTROLLER/
ADDITIONAL PINS OMITTED FOR CLARITY
PROCESSOR
UPPER BITS OF
ADDRESS BUS
DATABUS
DSP
1
R/W
D7
D0
A3
A2
A1
A0
Figure 32. AD7835 8-Bit Interface
ADDRESS
DECODE
DGND
D13
D8
AD7835
D7
D0
CS
LDAC
A2
A1
A0
BYSHF
WR
1
Rev. D | Page 22 of 28
When writing to the DACs, the lower eight bits must be written
first, followed by the upper six bits. The upper six bits should be
output on data lines D0 to D5. Once again, the upper address
lines of the processor are decoded to provide a
are also decoded in conjunction with lines A3 to A0 to provide
an
nal timing circuit or, if it is acceptable to allow the DAC output
to go to an intermediate value between 8-bit writes, LDAC can
be tied low.
Table 14. DAC Channel Decoding, 8-Bit Interface
A3
x
1
0
0
0
0
0
0
0
0
LDAC
Processor Address Lines
A2
X
X
0
0
0
0
1
1
1
1
signal. Alternatively,
A1
X
X
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
LDAC
DAC Selected
Upper 6 bits of all DACs
Lower 8 bits of all DACs
Upper 6 bits, DAC 1
Lower 8 bits, DAC 1
Upper 6 bits, DAC 2
Lower 8 bits, DAC 2
Upper 6 bits, DAC 3
Lower 8 bits, DAC 3
Upper 6 bits, DAC 4
Lower 8-bits, DAC 4
can be driven by an exter-
CS signal. They

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