AD9762 Analog Devices, AD9762 Datasheet - Page 16

• Manufacturer Part Number: AD9762
• Manufacturer: Analog Devices

Specifications of AD9762

• Resolution (bits): 12bit
• Dac Update Rate: 125MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9762
DIFFERENTIAL USING AN OP AMP
An op amp can also be used to perform a differential to single-
ended conversion as shown in Figure 51. The AD9762 is
configured with two equal load resistors, R
The differential voltage developed across I
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
I
addition of this capacitor also enhances the op amps distortion
performance by preventing the DACs high slewing output from
overloading the op amp’s input.
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ-
ential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off of a
dual supply since its output is approximately ± 1.0 V. A high
speed amplifier capable of preserving the differential perfor-
mance of the AD9762 while meeting other system level objec-
tives (i.e., cost, power) should be selected. The op amps
differential gain, its gain setting resistor values, and full-scale
output swing capabilities should all be considered when opti-
mizing this circuit.
The differential circuit shown in Figure 52 provides the neces-
sary level-shifting required in a single supply system. In this
case, AVDD which is the positive analog supply for both the
AD9762 and the op amp is also used to level-shift the differ-
ential output of the AD9762 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 53 shows the AD9762 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50 Ω cable since the nominal full-scale current, I
20 mA flows through the equivalent R
case, R
I
connected to ACOM directly or via a matching R
values of I
compliance range is adhered to. One additional consideration in
OUTA
OUTA
Figure 52. Single-Supply DC Differential Coupled Circuit
Figure 51. DC Differential Coupling Using an Op Amp
AD9762
and I
or I
LOAD
AD9762
IOUTA
IOUTB
OUTFS
OUTB
OUTB
represents the equivalent load resistance seen by
IOUTA
IOUTB
. The unused output (I
22
21
and R
forming a real pole in a low-pass filter. The
25
22
21
25
LOAD
C
OPT
C
can be selected as long as the positive
OPT
25
225
225
25
225
225
LOAD
OUTA
1k
OUTA
of 25 Ω. In this
500
AD8041
or I
LOAD
500
AD8047
OUTB
and I
1k
500
, of 25 Ω.
LOAD
) can be
OUTB
. Different
OUTFS
AVDD
is
, of
–16–
this mode is the integral nonlinearity (INL) as discussed in the
Analog Output section of this data sheet. For optimum INL
performance, the single-ended, buffered voltage output configu-
ration is suggested.
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 54 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9762 output current. U1 maintains I
virtual ground, thus minimizing the nonlinear output imped-
ance effect on the DAC’s INL performance as discussed in
the Analog Output section. Although this single-ended configu-
ration typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1’s slewing capabilities. U1 provides a negative
unipolar output voltage and its full-scale output voltage is sim-
ply the product of R
be set within U1’s voltage output swing capabilities by scaling
I
mance may result with a reduced I
U1 will be required to sink will be subsequently reduced.
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection;
placement and routing; and supply bypassing and grounding.
Figures 60–65 illustrate the recommended printed circuit board
ground, power and signal plane layouts which are implemented
on the AD9762 evaluation board.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9762 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physi-
cally possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close as physically as possible.
OUTFS
AD9762
Figure 53. 0 V to +0.5 V Unbuffered Voltage Output
and/or R
IOUTA
IOUTB
Figure 54. Unipolar Buffered Voltage Output
AD9762
IOUTA
IOUTB
22
21
FB
22
21
I
. An improvement in ac distortion perfor-
OUTFS
FB
I
OUTFS
and I
= 10mA
= 20mA
25
200
OUTFS
50
. The full-scale output should
OUTFS
C
200
R
U1
OPT
FB
since the signal current
OUTA
V
OUTA
(or I
50
V
= 0 TO +0.5V
OUT
OUTB
= I
OUTFS
) at a
REV. B
R
FB