AD7801 Analog Devices, AD7801 Datasheet - Page 11

• Manufacturer Part Number: AD7801
• Description: +2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7801

• Resolution (bits): 8bit
• Dac Update Rate: 833kSPS
• Dac Settling Time: 1.2µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

In the circuit shown the LDAC is hardwired low thus the DAC
output is updated on the rising edge of WR. Some applications
may require synchronous updating of the DAC in the AD7801.
In this case the LDAC signal can be driven from an external
timer or can be controlled by the microprocessor. One option
for synchronous updating is to decode the LDAC from the ad-
dress bus so a write operation at this address will synchronously
update the DAC output. A simple OR gate with one input
driven from the decoded address and the second input from the
WR signal will implement this function.
AD7801–8051/8088 Interface
Figure 31 shows a serial interface between the AD7801 and the
8051/8088 processors.
APPLICATIONS
Bipolar Operation Using the AD7801
The AD7801 has been designed for unipolar operation but
bipolar operation is possible using the circuit in Figure 32. The
circuit shown is configured for an output voltage range of –5 V
to +5 V. Rail-to-rail operation at the amplifier output is achievable
by using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
Where D is the decimal equivalent of the code loaded to the
DAC and V
With V
V
REV. 0
DD
8051/8088*
= 5 V.
V
PSEN OR DEN
REF
O
Figure 31. AD7801–8051/8088 Interface
= 2.5 V, R1 = R3 = 10 k and R2 = R4 = 20 k and
REF
R
2
ALE
AD7
AD0
A15
WR
A8
1
is the reference voltage input.
R4
R3
OCTAL
LATCH
*
/ R1 R2
ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
V
O
EN
ADDRESS BUS
10D
256
DATA BUS
DECODE
ADDR
2V
– 5
256
REF
D
V
CS
WR
LDAC
DB7
DB0
AD7801*
REF
R4
R3
–11–
Decoding Multiple AD7801s in a System
The CS pin on the AD7801 can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same input data, but only the CS to one of
the DACs will be active at any one time allowing access to one
channel in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the Enable input on the
74HC139 should be brought to its inactive state while the
Coded Address inputs are changing state. Figure 33 shows a
diagram of a typical setup for decoding multiple AD7801
devices in a system. The built-in power-on reset circuit on the
AD7801 ensures that the outputs of all DACs in the system
power up with zero volts on their outputs.
AD589 WITH V
EXT REF
AD780/REF192
WITH V
Figure 32. Bipolar Operation Using the AD7801
GND
V
ENABLE
CODED
ADDRESS
OR
WR
IN
DD
DATA BUS
= 5V
DD
V
Figure 33. Decoding Multiple AD7801s
OUT
= 3V
0.1 F
1G
1A
1B
74HC139
0.1 F
V
DD
DGND
V
V
10 F
DD
CC
REF IN
CLR
PD
D7-D0
DATA
BUS
1Y0
1Y1
1Y2
1Y3
V
DD
V
= 3V TO 5V
DD
AD7801
CONTROL
CS WR LDAC
INPUTS
AGND DGND
V
OUT
CS
WR
D0
D7
CS
WR
D0
D7
CS
WR
D0
D7
CS
WR
D0
D7
AD7801
AD7801
AD7801
AD7801
10k
R3
R1
10k
R2
20k
AD7801
LDAC
LDAC
LDAC
LDAC
AD820/
OP295
V
V
V
V
20k
OUT
OUT
OUT
OUT
R4
+5V
–5V
5V