AD7392 Analog Devices, AD7392 Datasheet - Page 14

• Manufacturer Part Number: AD7392
• Description: 3 V, Parallel Input Micropower 12-Bit DACs
• Manufacturer: Analog Devices

Specifications of AD7392

• Resolution (bits): 12bit
• Dac Update Rate: 17kSPS
• Dac Settling Time: 60µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

AD7392/AD7393
RESET PIN (RS)
Forcing the asynchronous RS pin low sets the DAC register to
all 0s, so the DAC output voltage is 0 V. The reset function is
useful for setting the DAC outputs to 0 at power-up or after a
power supply interruption. Test systems and motor controllers
are two of many applications that benefit from powering up to a
known state. The external reset pulse can be generated by three
methods:
•
•
•
RESET has a Schmitt-trigger input, which results in a clean
reset function when using external resistor-/capacitor-generated
pulses (see Table 6).
POWER SHUTDOWN (SHDN)
Maximum power savings can be achieved by using the power
shutdown control function. This hardware-activated feature is
controlled by the active low input SHDN pin. This pin has a
Schmitt-trigger input that helps desensitize it to slowly changing
inputs. Setting this pin to logic low reduces the internal con-
sumption of the AD7392/AD7393 to nanoamp levels, guaranteed
to 1.5 μA maximum over the operating temperature range. If
power is present at all times on the V
mode, the internal DAC register retains the last programmed
data value. The digital interface is still active in shutdown so
that code changes can be made that produce new DAC settings
when the device is taken out of shutdown. This data is used
when the part is returned to the normal active state by placing
the DAC back to its programmed voltage setting. Figure 23
shows a plot of shutdown recovery time with both I
displayed. In the shutdown state, the DAC output amplifier
exhibits an open-circuit high resistance state. Any load that is
connected stabilizes at its termination voltage. If the power
shutdown feature is not needed, the user should tie the SHDN
pin to the V
The microprocessor’s power-on RESET signal
An output from the microprocessor
An external resistor and capacitor
DD
voltage to disable this function.
DD
pin while in shutdown
DD
and V
OUT
Rev. C | Page 14 of 20
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7392. The
AD7392 is designed to drive loads as low as 5 kΩ in parallel
with 100 pF (see Figure 32). The code table for this operation is
shown in Table 7.
The circuit can be configured with an external reference
plus power supply or powered from a single dedicated regu-
lator or reference depending on the application performance
requirements.
Table 7. Unipolar Code Table
Hexadecimal
0xFFF
0x801
0x800
0x7FF
0x000
DAC Register No.
NOTES
1. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
EXT
REF
0.01µF
Figure 32. AD7392 Unipolar Output Operation
Decimal
4095
2049
2048
2047
0
20
R
V
2.7V TO 5.5V
REF
AD7392
Output Voltage (V), V
2.4994
1.2506
1.2500
1.2494
0
GND
V
DD
17, 18
1
V
OUT
19
R
≥5kΩ
0.1µF
L
REF
C
≥100pF
L
10µF
= 2.5 V