AD9764 Analog Devices, AD9764 Datasheet - Page 11

• Manufacturer Part Number: AD9764
• Manufacturer: Analog Devices

Specifications of AD9764

• Resolution (bits): 14bit
• Dac Update Rate: 125MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and I
varied by an external voltage, V
fier. An example of this method is shown in Figure 26 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V
referenced to ACOM and should not exceed 1.2 V. The value of
R
and 625 A, respectively. The associated equations in Figure 26
can be used to determine the value of R
In some applications, the user may elect to use an external
control amplifier to enhance the multiplying bandwidth,
distortion performance and/or settling time. External amplifiers
capable of driving a 50 pF load such as the AD817 are suitable
for this purpose. It is configured in such a way that it is in
parallel with the weaker internal reference amplifier as shown in
Figure 27. In this case, the external amplifier simply overdrives
the weaker reference control amplifier. Also, since the internal
control amplifier has a limited current output, it will sustain no
damage if overdriven.
REV. B
SET
Figure 27. Configuring an External Reference Control
Amplifier
is such that I
1 F
V
Figure 26. Dual-Supply Gain Control Circuit
GC
INPUT
V
REF
R
SET
CONTROL AMPLIFIER
R
SET
REFMAX
EXTERNAL
I
I
WITH V
REF
REF
AD1580
= (1.2–V
REFIO
FS ADJ
and I
GC
+1.2V REF
AD9764
REFIO
FS ADJ
1.2V
< V
+1.2V REF
AD9764
AVDD
GC
REFIO
REFLO
REFMIN
GC
)/R
REFLO
BANDLIMITING
SET
, applied to R
AND 62.5 A
CAPACITOR
OPTIONAL
50pF
do not exceed 62.5 A
OUT1
OUT2
SET
50pF
Figure 25. Single-Supply Gain Control Circuit
COMP1
.
AGND
I
R
REF
CURRENT
COMP1 AVDD
SOURCE
FB
AD7524
ARRAY
AVDD
CURRENT
SET
SOURCE
ARRAY
AVDD
625A
AVDD
DB7–DB0
via an ampli-
V
DD
V
REF
GC
REF
R
, is
SET
is
0.1V TO 1.2V
–11–
I
V
REF
REF
ANALOG OUTPUTS
The AD9764 produces two complementary current outputs,
I
or differential operation. I
complementary single-ended voltage outputs, V
V
Transfer Function section by Equations 5 through 8. The
differential voltage, V
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 28 shows the equivalent analog output circuit of the
AD9764 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of I
by the equivalent parallel combination of the PMOS switches
and is typically 100 k in parallel with 5 pF. Due to the na-
ture of a PMOS device, the output impedance is also slightly
dependent on the output voltage (i.e., V
a lesser extent, the analog supply voltage, AVDD, and full-scale
current, I
dency can be a source of dc nonlinearity and ac linearity (i.e.,
distortion), its effects can be limited if certain precautions are
noted.
I
ance range. The negative output compliance range of –1.0 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage and affect the reliability of the AD9764. The posi-
tive output compliance range is slightly dependent on the full-
scale output current, I
=
OUTA
/R
OUTA
OUTB
SET
and I
and I
, via a load resistor, R
REFIO
FS ADJ
Figure 28. Equivalent Analog Output Circuit
+1.2V REF
AD9764
OUTFS
OUTB
OUTB
REFLO
AD9764
BANDLIMITING
. Although the output impedance’s signal depen-
CAPACITOR
, which may be configured for single-end
also have a negative and positive voltage compli-
OPTIONAL
DIFF
50pF
OUTFS
, existing between V
OUTA
COMP1
. It degrades slightly from its nominal
LOAD
CURRENT
SOURCE
ARRAY
and I
AVDD
AVDD
, as described in the DAC
OUTA
OUTB
OUTA
and I
R
I
OUTA
LOAD
can be converted into
and V
OUTA
OUTB
AD9764
OUTA
OUTB
and V
is determined
I
R
OUTB
LOAD
AVDD
and
) and, to
OUTB