AD5554 Analog Devices, AD5554 Datasheet

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AD5554

Manufacturer Part Number
AD5554
Description
Quad, Current-Output, Serial-Input 16-/14-Bit DACs
Manufacturer
Analog Devices
Datasheet

Specifications of AD5554

Resolution (bits)
14bit
Dac Update Rate
500kSPS
Dac Settling Time
0.9µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Current Out
Dac Input Format
Ser,SPI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD5554BRS
Quantity:
3 100
Part Number:
AD5554BRSZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Data Sheet
FEATURES
AD5544: 16-bit resolution
AD5554: 14-bit resolution
2 mA full-scale current ± 20%, with V
0.9 µs settling time to ±0.1%
12 MHz multiplying bandwidth
Midscale glitch of −1 nV-sec
Midscale or zero-scale reset
4 separate, 4-quadrant multiplying reference inputs
SPI-compatible, 3-wire interface
Double-buffered registers enable
Simultaneous multichannel change
Internal power-on reset
Temperature range: −40°C to +125°C
Compact 28-lead SSOP and 32-lead LFCSP
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
GENERAL DESCRIPTION
The
to-analog converters (DACs) are designed to operate from a
2.7 V to 5.5 V supply range.
The applied external reference input voltage (V
the full-scale output current. Integrated feedback resistors (R
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
A double-buffered serial data interface offers high speed, 3-wire,
SPI- and microcontroller-compatible inputs using serial data in
(SDI), a chip select ( CS ), and clock (CLK) signals. In addition,
a serial data out pin (SDO) allows for daisy-chaining when multiple
packages are used. A common, level-sensitive, load DAC strobe
( LDAC ) input allows the simultaneous update of all DAC outputs
from previously loaded input registers. Additionally, an internal
power-on reset forces the output voltage to 0 at system turn-on.
The MSB pin allows system reset assertion ( RS ) to force all registers
to zero code when MSB = 0 or to half-scale code when MSB = 1.
Rev. F
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Trademarks and registered trademarks are the property of their respective owners.
INL of ±1 LSB (B Grade)
INL of ±0.5 LSB (B Grade)
AD5544/AD5554
quad, 16-/14-bit, current output, digital-
REF
= ±10 V
REF
x) determines
FB
)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Tel: 781.329.4700
Fax: 781.461.3113
Fax: 781.461.3113
The
lead LFCSP. The
SDO
CLK
SDI
CS
Serial-Input 16-/14-Bit DACs
AD5544
–0.1
–0.2
0.7
0.6
0.5
0.4
0.3
0.2
0.1
EN
DECODE
DGND
DAC A
0
2:4
D10
D11
D12
D13
D14
D15
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A0
A1
FUNCTIONAL BLOCK DIAGRAM
B
C
D
Figure 2.
is packaged in the compact 28-lead SSOP and 32-
16
10,000
AD5554
Quad, Current-Output,
©2000–2012 Analog Devices, Inc. All rights reserved.
©2000–2012 Analog Devices, Inc. All rights reserved.
POWER-ON
AD5544
REGISTER R
REGISTER R
REGISTER R
REGISTER R
RS
RESET
20,000
INPUT
INPUT
INPUT
INPUT
MSB
is packed in the compact 28-lead SSOP.
INL vs. Code Plot (T
30,000
Figure 1.
AD5544/AD5554
CODE
LDAC
REGISTER R
REGISTER R
REGISTER R
REGISTER R
40,000
DAC A
DAC B
DAC C
DAC D
50,000
A
V
= 25°C)
REF
AD5544
V
A B C
SS
www.analog.com
www.analog.com
60,000
DAC A
DAC B
DAC C
DAC D
D
70,000
V
R
I
A
R
I
A
R
I
A
R
I
A
A
OUT
OUT
OUT
OUT
DD
FB
GND
FB
GND
FB
GND
FB
GND
GND
A
B
C
D
A
B
C
D
A
B
C
D
F

Related parts for AD5554

AD5554 Summary of contents

Page 1

... Data Sheet FEATURES AD5544: 16-bit resolution INL of ±1 LSB (B Grade) AD5554: 14-bit resolution INL of ±0.5 LSB (B Grade full-scale current ± 20%, with V REF 0.9 µs settling time to ±0.1% 12 MHz multiplying bandwidth Midscale glitch of −1 nV-sec Midscale or zero-scale reset 4 separate, 4-quadrant multiplying reference inputs ...

Page 2

... TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AD5544 Electrical Characteristics ............................................. 3 AD5554 Electrical Characteristics ............................................. 4 Timing Diagrams .......................................................................... 6 Absolute Maximum Ratings ............................................................ 7 ESD Caution .................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 13 Digital-to-Analog Converter (DAC) ....................................... 13 Serial Data Interface ....................................................................... 15 Truth Tables ...

Page 3

... V DD Channel-to-channel Data = 0xFFFF Code dependent 100 µA OH Logic inputs = 0 V Logic inputs = − Rev Page AD5544/AD5554 full operating temperature REF A Min Typ Max Unit 16 Bits ±1 LSB ±2 LSB ±1 LSB ± ...

Page 4

... Typical values represent average readings measured at 25°C. 2 These parameters are guaranteed by design and not subject to production testing. 3 All input control signals are specified with All ac characteristic tests are performed in a closed-loop system using an AD5554 ELECTRICAL CHARACTERISTICS virtual GND OUT range of − ...

Page 5

... V) and timed from a voltage level of 1 AD8038 I-to-V converter amplifier,. Rev Page AD5544/AD5554 Min Typ 2.7 0.001 0 −1 −65 −90 0.6 −98 7 OP177 I-to-V converter amplifier. The AD5554 R Max Unit 5 µA 9 µA 1.25 mW 0.006 %/% µs MHz nV-sec dB dB nV-sec dB nV/√ ...

Page 6

... SDO Figure 3. AD5544 Timing Diagram D13 D12 D11 D10 D09 D08 SDO Figure 4. AD5554 Timing Diagram Rev Page Data Sheet D1 D0 INPUT REG LD t CSH t LDS t LDH t LDAC D1 D0 INPUT REG LD t CSH t LDS ...

Page 7

... affect device reliability. −0 0 −0.3 V, +0.3 V ±50 mA ESD CAUTION (T max − T )/θ θ JA 100°C/W 32.5°C/W 150°C −40°C to +125°C −65°C to +150°C 215°C 220°C Rev Page AD5544/AD5554 ...

Page 8

... REF GND LDAC REF C OUT C GND pin. DD AD5544 and 0x2000 for the AD5554), determined by the voltage on the MSB pin. pin. DD pin. DD AD5544 and 17 clock pulses for the Rev Page Data Sheet DGND GND ...

Page 9

... DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. This pin can be REF tied to the DAC D Current Output. OUT DAC D Analog Ground. GND N not connect. N not connect. N not connect. N not connect. N/A 33 EPAD Connect the exposed pad to AGNDx. pin. DD Rev Page AD5544/AD5554 ...

Page 10

... CODE Figure 8. AD5554 INL vs. Code, T 0.10 0.05 0 –0.05 –0.10 –0.15 0 2000 4000 6000 8000 10,000 CODE Figure 9. AD5554 DNL vs. Code, T 50,000 60,000 70,000 = 25°C A 12,000 14,000 16,000 18,000 = 25°C Figure 11. A 12,000 14,000 16,000 18,000 = 25°C A Rev Page ...

Page 11

... FREQUENCY (Hz) Figure 17. AD5544/AD5554 Power Supply Rejection vs. Frequency 20 0 –20 –40 –60 –80 –100 –120 –140 –160 0 5k 10k 15k FREQUENCY (Hz) Figure 18. AD5544/AD5554 Analog THD 10M 100M 10V REF 1M 20k 25k ...

Page 12

... AD5544/AD5554 300 250 200 150 100 0.5 1.0 1.5 2.0 2.5 3.0 LOGIC INPUT (V) Figure 19. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage 3.5 4.0 4.5 5.0 Rev Page Data Sheet ...

Page 13

... AD5544/AD5554 AD5544 and the AD5554 accommodate input OUT OUT OUT on the inverting input node of the amplifier. x and R OUT AD5544 and the AD5554, respectively. To maintain good AD5544/AD5554 2 0 –2 –4 –6 –8 100k 1M 10M FREQUENCY (Hz) Figure 21. AD5554 Reference Multiplying Bandwidth vs. Code ...

Page 14

... AD5544/AD5554 REF DIGITAL INTERFACE CONNECTIONS OMITTED. FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED, AND V MUST BE POWERED AD5544 5kΩ OUT A GND A GND FROM OTHER DACS A GND DGND Figure 22. Recommended Kelvin-Sensed Hookup Rev Page 15V ANALOG ...

Page 15

... D13 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers ...

Page 16

... High X High Low High 1 For the AD5554, data appears at the SDO pin 17 clock pulses after input at the SDI pin don’t care. 3 ↑ positive logic transition power-on, both the input register and the DAC register are loaded with all 0s. ...

Page 17

... The ideal power-up sequence power follows noncompliance power-up sequence may elevate the reference = 1 current, but the devices resume normal operation once V V are powered up. SS Rev Page AD5544/AD5554 REF DAC ...

Page 18

... DGND terminal should be joined remotely single point to the analog ground plane (see Figure 26). Rev Page Data Sheet AD5544/AD5554 10µF 0.1µ GND C4 C2 10µF 0.1µF V DGND SS x pins of the AD5544/AD5554 serve as GND ...

Page 19

... DAC. This is done by using low input capacitance buffer amplifiers and careful board design 5554 (4) Analog Devices offers a wide range of amplifiers for both precision dc and ac applications, as listed in Table 11 and Table 12. Rev Page AD5544/AD5554 . FB and AGND), they settle quickly. IN node (the voltage output node in this application) of REF ...

Page 20

... AD5544/AD5554 Table 10. Suitable Analog Devices Precision References Part No. Output Voltage (V) Initial Tolerance (%) ADR01 10 0.05 ADR01 10 0.05 ADR02 5.0 0.06 ADR02 5.0 0.06 ADR03 2.5 0.1 ADR03 2.5 0.1 ADR06 3.0 0.1 ADR06 3.0 0.1 ADR420 2.048 0.05 ADR421 2.50 0.04 ADR423 3.00 0.04 ADR425 5.00 0.04 ADR431 2.500 0.04 ADR435 5.000 0.04 ADR391 2.5 0.16 ADR395 5.0 0.10 Table 11. Suitable Analog Devices Precision Op Amps V OS Part No. Supply Voltage (V) (µ ...

Page 21

... The evaluation board requires ±12 V and +5 V supplies. The + and − are used to power the output DD SS amplifier, and the + used to power the DAC (DVDD). Figure 28. Evaluation Board Software—Device Selection Window page. Figure 29. Evaluation Board Rev Page AD5544/AD5554 Software—AD5544 Quad DAC ...

Page 22

... AD5544/AD5554 EVALUATION BOARD SCHEMATICS + + + + 13 Figure 30. EVAL-AD5544SDZ Schematic Part A Rev Page Data Sheet 00943-102 + 12 ...

Page 23

... PAR_D18 113 * PAR_D20 114 * PAR_D22 115 GND 116 VIO(+3.3V) 117 GND 118 GND 119 NC 120 NC Figure 31. EVAL-AD5544SDZ Schematic Part B Rev Page AD5544/AD5554 U10 VCC SCL 4 VSS 5 SDA 24LC64 /RS (connected to blackfin GPIO - use I2C_0 first) SCLK SDIN /CS SDO 3 ...

Page 24

... AD5544/AD5554 + + + + + + 7 Figure 32. EVAL-AD5544SDZ Schematic Part C Rev Page Data Sheet 00943-104 + + + 24 ...

Page 25

... Data Sheet EVALUATION BOARD LAYOUT Figure 33. Silkscreen Figure 34. Component Side Rev Page AD5544/AD5554 ...

Page 26

... AD5544/AD5554 Figure 35. Solder Side Rev Page Data Sheet ...

Page 27

... BSC 16 0.50 TOP VIEW 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 37. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ × Body, Very Very Thin Quad (CP-32-11) Dimensions shown in millimeters Rev Page AD5544/AD5554 0.25 0.09 8° 0.95 4° 0.75 0° 0. 3.65 EXPOSED PAD 3. ...

Page 28

... AD5544ACPZ-1-RL7 16 ±4 AD5544BCPZ-R2 16 ±1 AD5544BCPZ-RL7 16 ±1 AD5554BRSZ 14 ±0.5 EVAL-AD5544SDZ RoHS Compliant Part refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2000–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...

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