AD5336 Analog Devices, AD5336 Datasheet - Page 15
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AD5336
Manufacturer Part Number
AD5336
Description
Manufacturer
Analog Devices
Datasheet
1.AD5335.pdf
(20 pages)
Specifications of AD5336
Resolution (bits)
10bit
Dac Update Rate
143kSPS
Dac Settling Time
7µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Par
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REV. 0
CLR
1
1
0
1
1
1
1
1
X = don’t care.
CLR
1
1
0
1
1
1
1
1
1
1
1
1
X = don’t care.
POWER-ON RESET
The AD5334/AD5335/AD5336/AD5344 are provided with a
power-on reset function, so that they power up in a defined state.
The power-on state is:
• Normal operation
• 0 – V
• Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
POWER-DOWN MODE
The AD5334/AD5335/AD5336/AD5344 have low power con-
sumption, dissipating typically 1.5 mW with a 3 V supply and
3 mW with a 5 V supply. Power consumption can be further
reduced when the DACs are not in use by putting them into
power-down mode, which is selected by taking pin PD low.
REF
LDAC
1
1
X
1
1
1
1
0
LDAC
1
1
X
1
1
1
1
1
1
1
1
0
output range
Figure 30. Data Format For AD5335
X = UNUSED BIT
DB7
X
DB6
X
CS
1
X
X
0
0
0
0
0
0
0
0
X
DB5
CS
1
X
X
0
0
0
0
X
X
HIGH BYTE
LOW BYTE
DB4
X
DB3
X
WR
X
1
X
0➝1
0➝1
0➝1
0➝1
0➝1
0➝1
0➝1
0➝1
X
WR
X
1
X
0➝1
0➝1
0➝1
0➝1
X
DB2
X
DB9
DB1
Table I. AD5334/AD5336/AD5344 Truth Table
A1
X
X
X
0
0
0
0
1
1
1
1
X
DB0
DB8
A1
X
X
X
0
0
1
1
X
Table II. AD5335 Truth Table
A0
X
X
X
0
0
1
1
0
0
1
1
X
A0
X
X
X
0
1
0
1
X
–15–
HBEN
X
X
X
0
1
0
1
0
1
0
1
X
When the PD pin is high, the DACs work normally with a typical
power consumption of 600 µA at 5 V (500 µA at 3 V). In power-
down mode, however, the supply current falls to 200 nA at 5 V
(80 nA at 3 V) when the DACs are powered down. Not only
does the supply current drop, but the output stage is also internally
switched from the output of the amplifier, making it open-circuit.
This has the advantage that the outputs are three-state while
the part is in power-down mode, and provides a defined input
condition for whatever is connected to the outputs of the
DAC amplifiers. The output stage is illustrated in Figure 31.
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for V
V
to when the output voltage deviates from its power-down volt-
age. See Figure 22.
DD
Function
No Data Transfer
No Data Transfer
Clear All Registers
Load DAC A Input Register, GAIN A (AD5334/AD5336)
Load DAC B Input Register, GAIN B (AD5334/AD5336)
Load DAC C Input Register, GAIN C (AD5334/AD5336)
Load DAC D Input Register, GAIN D (AD5334/AD5336)
Update DAC Registers
= 3 V. This is the time from a rising edge on the PD pin
AD5334/AD5335/AD5336/AD5344
Figure 31. Output Stage During Power-Down
STRING DAC
RESISTOR
Function
No Data Transfer
No Data Transfer
Clear All Registers
Load DAC A Low Byte Input Register
Load DAC A High Byte Input Register
Load DAC B Low Byte Input Register
Load DAC B High Byte Input Register
Load DAC C Low Byte Input Register
Load DAC C High Byte Input Register
Load DAC D Low Byte Input Register
Load DAC D High Byte Input Register
Update DAC Registers
AMPLIFIER
DD
POWER-DOWN
CIRCUITRY
= 5 V and 5 µs when
V
OUT