AD5317 Analog Devices, AD5317 Datasheet - Page 5

• Manufacturer Part Number: AD5317
• Manufacturer: Analog Devices

Specifications of AD5317

• Resolution (bits): 10bit
• Dac Update Rate: 143kSPS
• Dac Settling Time: 7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AC CHARACTERISTICS
V
Table 2.
Parameter
Output Voltage Settling Time
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
SDO Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1
2
3
TIMING CHARACTERISTICS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization; not production tested.
See the Terminology section.
Guaranteed by design and characterization; not production tested.
All input signals are specified with t
See Figure 3 and Figure 4.
This is measured with the load circuit of Figure 2. t
Daisy-chain mode only.
DD
DD
4, 5
AD5307
AD5317
AD5327
= 2.5 V to 5.5 V, R
= 2.5 V to 5.5 V; all specifications T
2, 3
1, , 2
A, B Versions
Limit at T
33
13
13
13
5
4.5
5
50
20
20
20
0
20
25
5
8
0
L
= 2 kΩ to GND, C
MIN
R
, T
= t
MAX
F
= 5 ns (10% to 90% of V
MIN
13
L
to T
= 200 pF to GND. All specifications T
determines maximum SCLK frequency in daisy-chain mode.
Min
MAX
A, B Versions
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
, unless otherwise noted.
Typ
6
7
8
0.7
12
0.5
4
0.5
1
3
200
−70
DD
) and timed from a voltage level of (V
Rev. C | Page 5 of 28
Max
8
9
10
1
Conditions/Comments
SCLK cycle time
SCLK low time
SYNC to SCLK falling edge set-up time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width
SCLK falling edge to LDAC rising edge
CLR pulse width
SCLK falling edge to LDAC falling edge
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
SCLK high time
Data set-up time
Data hold time
SCLK rising edge to SDO valid (V
SCLK rising edge to SDO valid (V
Unit
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Conditions/Comments
V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
Daisy-chain mode; SDO load is 10 pF
V
V
MIN
REF
REF
REF
= V
= 2 V ± 0.1 V p-p; unbuffered mode
= 2.5 V ± 0.1 V p-p; frequency = 10 kHz
to T
IL
+ V
DD
MAX
IH
= 5 V
)/2.
, unless otherwise noted.
DD
DD
AD5307/AD5317/AD5327
= 3.6 V to 5.5 V)
= 2.5 V to 3.5 V)