AD5532B Analog Devices, AD5532B Datasheet - Page 8

• Manufacturer Part Number: AD5532B
• Description: 32-Channel 14-bit Bipolar Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5532B

• Resolution (bits): 14bit
• Dac Update Rate: 45kSPS
• Dac Settling Time: 22µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5532B
Mnemonic
AGND (1–2)
AV
V
V
DGND
DV
DAC_GND (1–2)
REF_IN
REF_OUT
V
V
A4–A1
CAL
CS/SYNC
WR
OFFSET_SEL
SCLK
D
D
SER/PAR
OFFS_IN
OFFS_OUT
BUSY
TRACK/RESET
NOTES
1
2
Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
DD
SS
OUT
IN
IN
OUT
CC
CC
1
2
(1–4)
(1–4)
1
(0–31)
(1–2)
Figure 6. DAC Transfer Function (OFFS_IN = 0)
2
1
ERROR RANGE
, A0
FULL-SCALE
1
VOLTAGE
2
OUTPUT
OFFSET
RANGE
1
2
0
Description
Analog GND Pins
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
V
V
Digital GND Pins
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
Reference GND Supply for all the DACs
Reference Voltage for Channels 0–31
Reference Output Voltage
Analog Output Voltages from the 32 Channels
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB.
Parallel Interface. Control input that allows all 32 channels to acquire V
This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for
the serial interface.
Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to address the device
using the parallel interface.
Parallel Interface. Offset select pin. Active high. This is used to select the offset channel.
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode).
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid
on the falling edge of SCLK.
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,
the parallel interface will be used. If it is tied high, the serial interface will be used.
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to
this pin if the user wants to drive this pin with the offset channel.
Offset Output. This is the acquired/programmed offset voltage that can be tied to OFFS_IN to offset the span.
This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns
high when the acquisition operation is complete.
If this input is held high, V
gain/offset stage is switched directly to V
of TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going
pulse of between 90 ns and 200 ns to this pin. See section on RESET Function for further details.
IDEAL GAIN
DD
SS
Supply Pins. Voltage range from –4.75 V to –16.5 V.
Supply Pins. Voltage range from 8 V to 16.5 V.
DAC CODE
IDEAL TRANSFER
FUNCTION
50mV
IDEAL GAIN
16k
PIN FUNCTION DESCRIPTIONS
IN
REFIN
is acquired once the channel is addressed. While it is held low, the input to the
–8–
IN
. The addressed channel begins to acquire V
V
OUT
0V
DEAD BAND
OFFSET
LOWER
ERROR
Figure 7. ISHA Transfer Function
70mV
TRANSFER
FUNCTION
IDEAL
IN
simultaneously.
ACTUAL
TRANSFER
FUNCTION
DEAD BAND
IN
2.96 3V
UPPER
on the rising edge
GAIN ERROR +
OFFSET ERROR
V
IN
REV. A