AD5405 Analog Devices, AD5405 Datasheet
AD5405
Specifications of AD5405
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AD5405 Summary of contents
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... This DAC uses data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s, and the DAC outputs are at zero scale. The AD5405 has × 6 mm, 40-lead LFCSP package. 1 U.S. Patent Number 5,689,257. FUNCTIONAL BLOCK DIAGRAM ...
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... AD5405 TABLE OF CONTENTS Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 13 General Description ....................................................................... 14 DAC Section ................................................................................ 14 Circuit Operation ....................................................................... 14 Single-Supply Applications ....................................................... 15 Adding Gain ................................................................................ 15 REVISION HISTORY 12/09—Rev Rev. B Changes to Figure 1 .......................................................................... 1 Changes to Table 2 and Figure 2 ..................................................... 5 Changes to Table 4 and Figure 4 ...
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... DAC latch alternately loaded with 0s and 1s Interface time delay Rise and fall times 1 LSB change around major carry REF DAC latch loaded with all 0s ±3.5 V REF 1 MHz 10 MHz DAC latches loaded with all 0s DAC latches loaded with all 1s AD5405 , unless 1 ...
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... AD5405 Parameter Digital Feedthrough Output Noise Spectral Density Analog THD Digital THD 100 kHz f OUT 50 kHz f OUT SFDR Performance (Wideband) Clock = 10 MHz 500 kHz f OUT 100 kHz f OUT 50 kHz f OUT Clock = 25 MHz 500 kHz f OUT 100 kHz f OUT 50 kHz f OUT SFDR Performance (Narrow Band) ...
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... (MIN) OUTPUT C PIN L 50pF 200 μ Figure 3. Load Circuit for Data Timing Specifications Rev Page )/ 2 5 unless otherwise noted. MIN MAX (MAX) 2 AD5405 ...
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... AD5405 ABSOLUTE MAXIMUM RATINGS Transient currents 100 mA do not cause SCR latch-up 25°C, unless otherwise noted. A Table 3. Parameter V to GND GND REF REF GND OUT OUT 1 Logic Inputs and Output Operating Temperature Range ...
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... R3A AD5405 REF DGND 6 TOP VIEW LDAC 7 (Not to Scale) DAC A DB11 10 NOTES CONNECT. 2. EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 4. Pin Configuration Rev Page R1B 29 R2B 28 R2_3B 27 R3B REF CLR 23 R DB0 AD5405 ...
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... AD5405 TYPICAL PERFORMANCE CHARACTERISTICS 1 25° 10V REF 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE Figure 5. INL vs. Code (12-Bit DAC) 1 25° 10V REF 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 ...
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... REF C = ±2V, AD8038 C V 1pF REF C = ±0.15V, AD8038 C V 1pF REF C = ±0.15V, AD8038 C V 1.47pF REF C = ±3.51V, AD8038 C V 1.8pF REF C 100k 1M 10M FREQUENCY (Hz) and Compensation Capacitor AD5405 T = 25° ±3.5V = 1.8pF 10M 100M 100M 100M ...
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... AD5405 0.045 0x7FF TO 0x800 0.040 0.035 0.030 0.025 0.020 0.015 0x800 TO 0x7FF 0.010 0.005 0 –0.005 –0.010 100 120 TIME (ns) Figure 17. Midscale Transition, V –1.68 0x7FF TO 0x800 –1. –1.70 –1.71 –1. –1. – ...
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... CODES 100 110 120 130 140 FREQUENCY (kHz) = 100 kHz, Clock = 25 MHz OUT T = 25° AMP = AD8038 65k CODES 100 105 110 115 FREQUENCY (kHz kHz, 100 kHz, Clock = 10 MHz OUT AD5405 750 150 120 ...
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... AD5405 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 FREQUENCY (kHz) Figure 29. Wideband IMD kHz, 100 kHz, Clock = 25 MHz OUT 300 T = 25° AMP = AD8038 250 65k CODES 200 150 100 ...
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... IMD is defined as = IMD 20 log Compliance Voltage Range The maximum range of (output) terminal voltage for which the device provides the specified characteristics. Rev Page AD5405 1 terminal when all 0s are OUT + + + ...
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... AD5405 GENERAL DESCRIPTION DAC SECTION The AD5405 is a 12-bit, dual-channel, current-output DAC consisting of a standard inverting R-2R ladder configuration. Figure 31 shows a simplified diagram for a single channel of the AD5405. The feedback resistor R A has a value of 2R. The FB value typically 10 kΩ (with a minimum of 8 kΩ and a maximum of 13 kΩ ...
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... V A 12-BIT DAC REF I 2A OUT GND –5V NOTES 1. SIMILAR CONFIGURATION FOR DAC PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED HIGH SPEED AMPLIFIER. Figure 35. Positive Voltage Output with Minimum Components resistor causes mismatches FB AD5405 polarity for REF +2.5V OUT ...
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... AD5405 OUT V 12-BIT REF DAC I 2A OUT GND NOTES 1. SIMILAR CONFIGURATION FOR DAC PHASE COMPENSATION (1pF TO 2pF REQUIRED HIGH SPEED AMPLIFIER. Figure 36. Increasing Gain of Current Output DAC DIVIDER OR PROGRAMMABLE GAIN ELEMENT Current-steering DACs are very flexible and lend themselves to many applications ...
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... VOS (Max) (μV) I (Max) (nA) Package B 1,500 6,000 SOIC-8, SOT-23, MSOP 1,000 10,500 SOIC-8, MSOP 3,000 750 SOIC-8, SC70-5 10,000 7,000 SOIC-8 AD5405 T Package SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23 , SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 SOIC-8 TSOT-23 TSOT-23 Package SOIC-8 ...
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... AD5405 PARALLEL INTERFACE Data is loaded into the AD5405 in a 12-bit parallel word format. Control lines CS and R/ W allow data to be written to or read from the DAC register. A write event takes place when CS and R/ W are brought low, data available on the data lines fills the shift register, and the rising edge of CS latches the data and transfers the latched data-word to the DAC register ...
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... The printed circuit board on which the AD5405 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only ...
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... AD5405 Figure 41. Schematic of AD5405 Evaluation Board Figure 42. Component-Side Artwork Rev Page ...
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... Figure 43. Silkscreen—Component-Side View (Top Layer) Figure 44. Solder-Side Artwork Rev Page AD5405 ...
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... AD5429 8 2 AD5450 8 1 AD5432 10 1 AD5433 10 1 AD5439 10 2 AD5440 10 2 AD5451 10 1 AD5443 12 1 AD5444 12 1 AD5415 12 2 AD5405 12 2 AD5445 12 2 AD5447 12 2 AD5449 12 2 AD5452 12 1 AD5446 14 1 AD5453 14 1 AD5553 14 1 AD5556 14 1 AD5555 14 2 AD5557 ...
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... PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Resolution AD5405YCP 12 AD5405YCP–REEL 12 AD5405YCP–REEL7 12 AD5405YCPZ 12 AD5405YCPZ–REEL 12 AD5405YCPZ–REEL7 12 EVAL-AD5405EB RoHS Compliant Part. 0.60 MAX 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.23 0.08 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ × ...
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... AD5405 NOTES © 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04463–0–12/09(B) Rev Page ...