AD5382 Analog Devices, AD5382 Datasheet - Page 23

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AD5382

Manufacturer Part Number
AD5382
Description
32-Channel 14-Bit 3 V/5 V Single-Supply Voltage-Output DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD5382

Resolution (bits)
14bit
Dac Update Rate
125kSPS
Dac Settling Time
8µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Par,Ser,SPI

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Table 16. Control Register Contents
MSB
CR13
Control Register Write/Read
REG1 = REG0 = 0, A4–A0 = 01100, R/ W status determines
if the operation is a write (R/ W = 0) or a read (R/ W = 1).
DB13 to DB0 contain the control register data.
Control Register Contents
CR13: Power-Down Status. This bit is used to configure the
output amplifier state in power-down.
CR12: REF Select. This bit selects the operating internal
reference for the AD5382.
CR11: Current Boost Control. This bit is used to boost the
current in the output amplifier, thereby altering its slew rate.
CR10: Internal/External Reference. This bit determines
if the DAC uses its internal reference or an externally
applied reference.
CR9: Channel Monitor Enable (see Channel Monitor Function)
CR13 = 1. Amplifier output is high impedance (default on
power-up).
CR13 = 0. Amplifier output is 100 kΩ to ground.
CR12 = 1: Internal reference is 2.5 V (AD5382-5 default), the
recommended operating reference for AD5382-5.
CR12 = 0: Internal reference is 1.25 V (AD5382-3 default),
the recommended operating reference for AD5382-3.
CR11 = 1: Boost Mode On. This maximizes the bias current
in the output amplifier, optimizing its slew rate but increasing
the power dissipation.
CR11 = 0: Boost Mode Off (default on power-up). This
reduces the bias current in the output amplifier and reduces
the overall power consumption.
CR10 = 1: Internal Reference Enabled. The reference output
depends on data loaded to CR12.
CR10 = 0: External Reference Selected (default on power-up).
CR9 = 1: Monitor Enabled. This enables the channel monitor
function. After a write to the monitor channel in the SFR
register, the selected channel output is routed to the
MON_OUT pin.
CR9 = 0: Monitor Disabled (default on power-up). When the
monitor is disabled, MON_OUT is three-stated.
CR12
CR11
CR10
CR9
CR8
Rev. B | Page 23 of 40
CR7
CR8: Thermal Monitor Function. This function is used to
monitor the AD5382’s internal die temperature when enabled.
The thermal monitor powers down the output amplifiers when
the temperature exceeds 130°C. This function can be used to
protect the device when power dissipation may be exceeded if a
number of output channels are simultaneously short-circuited.
A soft power-up re-enables the output amplifiers if the die
temperature drops below 130°C.
CR7 and CR6: Don’t Care.
CR5 to CR2: Toggle Function Enable. This function allows the
user to toggle the output between two codes loaded to the A
and B register for each DAC. Control Register Bits CR5 to CR2
are used to enable individual groups of eight channels for
operation in toggle mode. A Logic 1 written to any bit enables a
group of channels; a Logic 0 disables a group. LDAC is used to
toggle between the two registers.
for toggle contains Channels 24 to 31, CR5 = 1 enables these
channels.
Table 17.
CR Bit
CR5
CR4
CR3
CR2
CR1 and CR0: Don’t Care.
Channel Monitor Function
REG1 = REG0 = 0, A4–A0 = 01010
DB13–DB8 = Contain data to address the monitored channel
A channel monitor function is provided on the AD5382.
This feature, which consists of a multiplexer addressed via the
interface, allows any channel output or the signals connected
to the MON_IN inputs to be routed to the MON_OUT pin for
monitoring using an external ADC. The channel monitor func-
tion must be enabled in the control register before any channels
are routed to MON_OUT. On the AD5382, DB13 to DB8
contain the channel address for the monitored channel.
Selecting channel address 63 three-states MON_OUT.
CR6
CR8 = 1: Thermal Monitor Enabled.
CR8 = 0: Thermal Monitor Disabled (default on power-up).
CR5
CR4
Group
3
2
1
0
CR3
Table 17
CR2
shows the decoding
Channels
24–31
16–23
8–15
0–7
CR1
AD5382
LSB
CR0

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