AD5641 Analog Devices, AD5641 Datasheet - Page 13

• Manufacturer Part Number: AD5641
• Description: 2.7 V to 5.5 V,
• Manufacturer: Analog Devices

Specifications of AD5641

• Resolution (bits): 14bit
• Dac Update Rate: 1.7MSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Data Sheet
THEORY OF OPERATION
DIGITAL-TO-ANALOG SECTION
The AD5641 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 33 is a block diagram of the DAC
architecture.
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
where D is the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 16,384.
RESISTOR STRING
The resistor string structure is shown in Figure 34. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
DAC REGISTER
V
OUT

V
DD
R
R
R
R
R
Figure 34. Resistor String Structure

Figure 33. DAC Architecture

 

16
,
D
384

 

RESISTOR
NETWORK
REF (+)
REF (–)
GND
V
DD
TO OUTPUT
AMPLIFIER
OUTPUT
AMPLIFIER
V
Rev. D | Page 13 of 20
OUT
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to V
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 21. The slew rate is 0.5 V/μs, with a
midscale settling time of 8 μs with the output loaded.
SERIAL INTERFACE
The AD5641 has a 3-wire serial interface ( SYNC , SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the SDIN line is clocked into the 16-bit shift register on
the falling edge of SCLK. The serial clock frequency can be as
high as 30 MHz, making the AD5641 compatible with high
speed DSPs. On the 16
clocked in and the programmed function is executed (a change
in DAC register contents and/or a change in the mode of
operation). At this stage, the SYNC line can be kept low or
brought high. In either case, it must be brought high for a
minimum of 20 ns before the next write sequence, so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when V
than it does when V
write sequences for even lower power operation of the part, as
previously mentioned. However, it must be brought high again
just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 35). The first
two bits are control bits, which determine the operating mode
of the part (normal mode or any one of three power-down modes).
For a complete description of the various modes, see the Power-
Down Modes section. The next 14 bits are the data bits, which
are transferred to the DAC register on the 16
of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16
16
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 36).
th
th
falling edge. However, if SYNC is brought high before the
falling edge, this acts as an interrupt to the write sequence.
IN
= 0.8 V, SYNC should be idled low between
th
falling clock edge, the last data bit is
th
falling edge
AD5641
IN
= 1.8 V
DD
. It is