AD5452 Analog Devices, AD5452 Datasheet - Page 23

• Manufacturer Part Number: AD5452
• Description: 12-Bit High Bandwidth Multiplying DACs with Serial Interface
• Manufacturer: Analog Devices

Specifications of AD5452

• Resolution (bits): 12bit
• Dac Update Rate: 2.7MSPS
• Dac Settling Time: 160ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

Th
serial ports (SPORT). A serial interface between the DAC and
the
enabled, initiate transmission by writing a word to the Tx
re
D
register upon the falling edge its SCLK. The
updated by using the transmit frame synchronization (TFS) li
to provide a SYNC signal.
80C51/80L51-to-AD5450/AD5451/AD5452/AD5453
Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 60. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line,
SDIN. P1.1
to drive SYNC
low. The 80C51/80L51 transmit data only in 8-bit bytes; there-
fore, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller upon the rising edge of TxD and is valid upon
th
DAC and microcontroller interface. P1.1 is taken high followin
the completion of this cycle. The 80C51/80L51 provide the LSB
of its SBUF register as the first bit in the data stream. The DAC
input register acquires its data with the MSB as the first bit received
The transmit routine should take this into account.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 59. AD
SP’s serial clock and clocked into the DAC’s input shift
gister. The data is clocked out upon each rising edge of the
e falling edge. As a result, no glue logic is required between the
Figure 5
e ADSP-BF
ADSP-BF5xx*
ADSP-BF5xx*
DSP SPOR
8. AD
is a bit-programmable pin on the serial port and is used
SP-BF5xx SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface
SPIxSEL
SP-BF5xx-to-AD545
SCLK
MOSI
5xx proc
. As data is transmitted to the switch, P1.1 is taken
T is show
SCK
TFS
DT
essor inco
n in Figu
0/AD5451/AD5452/AD5453 Interface
rporates channel synchron s
re 59. When the SPORT is
AD5452/AD5453*
SYNC
SDIN
SCLK
AD5450/AD5451/
SYNC
SDIN
SCLK
DAC output is
AD5452/AD5453*
AD5450/AD5451/
ou
Rev. E | Page 23 of 32
ne
g
.
M
Interfac
Figure 61 is an example of a serial interface between the DAC
and the M
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the DAC.
The SYNC
is being transmitted to the AD5450/AD5451/AD5452/AD5453,
the SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid upon the falling edge of SCK. Serial data from the
68HC11 is
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the DAC, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is performed
to the DAC. PC7 is taken high at the end of this procedure.
If the us
input sh
the MC
regist
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PIN
MC68HC11*
C68HC
Figure 60. 80C51/80L51-to-AD5450/AD5451/AD5452/AD5453 Interface
8051*
Figu
er clocks
re 61. M
68HC
er wa
ift reg
e
11-to-AD5450/AD5
C68HC11 microcontroller. The serial peripheral
transmitted in 8-bit bytes with only eight falling
signal is derived from a port line (PC7). When data
AD5450/AD5451/AD5452/AD5453
C68
nts t
11.
S OMITTED
ister
MOSI
da
P1.1
RxD
SCK
TxD
PC7
HC11-to-AD54
In this conf
ta out upon t
o verify th
, the SDO l
FOR CL
e data previously written
ARITY
iguration with
50/AD5451/AD5452/A
ine can be connecte
he rising edges of SCLK.
451/AD5452/AD5453
SCLK
SDIN
SYNC
SYNC low, the shift
AD5452/AD5453*
SYNC
SCLK
SDIN
AD5450/AD5451/
AD5450/AD5451/
AD5452/AD5453*
D5453 Interface
d to MISO of
to the
clock