AD5678 Analog Devices, AD5678 Datasheet

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AD5678

Manufacturer Part Number
AD5678
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD5678

Resolution (bits)
16bit
Dac Update Rate
95kSPS
Dac Settling Time
6µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5678ARUZ-2
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD5678BRUZ-1
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD5678YRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
FEATURES
Low power octal DAC with
14-lead/16-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
3 power-down functions
Hardware LDAC and LDAC override function
CLR function to programmable code
Rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5678 is a low power, octal, buffered voltage-output
DAC with four 12-bit DACs and four 16-bit DACs in a single
package. All devices operate from a single 2.7 V to 5.5 V supply
and are guaranteed monotonic by design.
The AD5678 has an on-chip reference with an internal gain of 2.
The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full-
scale output of 2.5 V; the AD5678-2 has a 2.5 V 5 ppm/°C
reference, giving a full-scale output of 5 V. The on-board
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a software write.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V and remains powered up at
this level until a valid write takes place. The part contains a
power-down feature that reduces the current consumption of
the device to 400 nA at 5 V and provides software-selectable
output loads while in power-down mode for any or all DAC
channels.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Four 16-bit DACs
Four 12-bit DACs
4 × 12-Bit and 4 × 16-Bit Octal DAC with
On-Chip Reference in 14-Lead TSSOP
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SYNC
The outputs of all DACs can be updated simultaneously using
the LDAC function, with the added functionality of user-
selectable DAC channels to simultaneously update. There is
also an asynchronous CLR that clears all DACs to a software-
selectable code—0 V, midscale, or full scale.
The AD5678 utilizes a versatile 3-wire serial interface that
operates at clock rates of up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards. The on-chip precision output amplifier enables rail-
to-rail output swing.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
SCLK
DIN
1
RU-16 PACKAGE ONLY
AD5678
Octal DAC (four 12-bit DACs and four 16-bit DACs).
On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
Available in 14-lead/16-lead TSSOP.
Power-on reset to 0 V.
Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
LDAC
INTERFACE
LOGIC
LDAC
1
FUNCTIONAL BLOCK DIAGRAM
CLR
1
©2005–2011 Analog Devices, Inc. All rights reserved.
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
POWER-ON
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
RESET
V
DD
Figure 1.
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
V
REFIN
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
/V
REFOUT
1.25V/2.5V
REF
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
AD5678
www.analog.com
POWER-DOWN
LOGIC
GND
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
A
B
C
D
E
F
G
H

Related parts for AD5678

AD5678 Summary of contents

Page 1

... The AD5678 has an on-chip reference with an internal gain of 2. The AD5678-1 has a 1. ppm/°C reference, giving a full- scale output of 2.5 V; the AD5678-2 has a 2 ppm/°C reference, giving a full-scale output The on-board reference is off at power-up, allowing the use of an external reference ...

Page 2

... AD5678 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Characteristics........................................................................ 7 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 18 Theory of Operation ...................................................................... 20 REVISION HISTORY 2/11—Rev Rev. C Changes to Zero-Code Error Parameter and Offset Error Parameter, Table 1 ...

Page 3

... SPECIFICATIONS kΩ to GND Table 1. Parameter Min 2 STATIC PERFORMANCE AD5678 (DAC Resolution 12 Relative Accuracy Differential Nonlinearity AD5678 (DAC Resolution 16 Relative Accuracy Differential Nonlinearity Zero-Code Error Zero-Code Error Drift Full-Scale Error Gain Error Gain Temperature ...

Page 4

... Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,064) and AD5678 16-bit DACs (Code 512 to Code 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive ...

Page 5

... kΩ to GND Table 2. Parameter Min STATIC PERFORMANCE 2 AD5678 (DAC Resolution 12 Relative Accuracy Differential Nonlinearity AD5678 (DAC Resolution 16 Relative Accuracy Differential Nonlinearity Zero-Code Error Zero-Code Error Drift Full-Scale Error Gain Error Gain Temperature Coefficient ...

Page 6

... Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,064) and AD5678 16-bit DACs (Code 512 to Code 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive ...

Page 7

... V ± 0.1 V p-p, frequency = MHz REF 0.5 nV-s 2.5 nV-s 3 nV-s 340 kHz ± 0.2 V p-p REF − ± 0.1 V p-p, frequency = 10 kHz REF 120 nV/√Hz DAC code = 0x8400, 1 kHz 100 nV/√Hz DAC code = 0x8400, 10 kHz 15 μV p-p 0 Rev Page AD5678 unless otherwise noted. MIN MAX 3 ...

Page 8

... AD5678 TIMING CHARACTERISTICS All input signals are specified with ns/V (10 5.5 V. All specifications T DD Table 4. Limit MIN MAX Parameter ...

Page 9

... DD + 0.3 V other conditions above those indicated in the operational DD section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. − T )/θ J MAX A JA Rev Page AD5678 ...

Page 10

... Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. The AD5678 has a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin ...

Page 11

... Figure 10. DNL—16-Bit DAC, 1.25 V Internal Reference Rev Page 2.5V REFOUT T = 25°C A CODE Figure 8. DNL 16-Bit DAC, 2.5 V Internal Reference 1.25V REFOUT T = 25°C A CODE 1.25V REFOUT T = 25°C A CODE AD5678 ...

Page 12

... AD5678 1 REF T = 25°C 0.8 A 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE Figure 11. INL—12-Bit DAC 0. REF T = 25°C A 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0 500 1000 1500 2000 2500 CODE Figure 12. DNL—12-Bit DAC 1 ...

Page 13

... 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44 80 100 Figure 21 REFOUT 5.2 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28 Figure 22. I Rev Page AD5678 ZERO-SCALE ERROR OFFSET ERROR 3.2 3.7 4.2 4.7 5 (mA) DD Histogram with External Reference 1.25V V = 2.5V REFOUT I (mA) DD Histogram with Internal Reference ...

Page 14

... Figure 24. AD5678-2 Source and Sink Capability 4. 1.25V REFOUT T = 25°C A 3.00 3/4 SCALE 2.00 MIDSCALE 1.00 1/4 SCALE 0 –1.00 –30 –20 –10 0 CURRENT (mA) Figure 25. AD5678-1 Source and Sink Capability FULL SCALE ZERO SCALE FULL SCALE ZERO SCALE Rev Page 2 25° ...

Page 15

... MAX(C2)* 2.489 420.0mV 2.488 2.487 2.486 2.485 0 8.0ns/pt Figure 34. Digital-to-Analog Glitch Impulse (Negative) Rev Page AD5678 REF T = 25° OUT CH2 1.0V M100μs 125MS/s 8.0ns/pt A CH1 1.28V Fig ure 32 ...

Page 16

... AD5678 2.5000 2.4995 2.4990 2.4985 2.4980 2.4975 2.4970 2.4965 2.4960 2.4955 2.4950 0 64 128 192 256 SAMPLE Figure 35. Analog Crosstalk 2.4900 2.4895 2.4890 2.4885 2.4880 2.4875 2.4870 2.4865 2.4860 2.4855 0 64 128 192 256 SAMPLE Figure 36. DAC-to-DAC Crosstalk ...

Page 17

... Figure 42. Settling Time vs. Capacitive Load 10k CH3 5. –5 –10 –15 –20 5V –25 –30 –35 – 10k Rev Page AD5678 CLR V F OUT V B OUT CH2 1.0V M200ns A CH3 1.10V CH4 1.0V Figure 43. Hardware CLR 25°C A 100k 1M FREQUENCY (Hz) Figure 44. Multiplying Bandwidth ...

Page 18

... DAC register. Ideally, the output should The zero-code error is always positive in the AD5678, because the output of the DAC cannot go below due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in millivolts. ...

Page 19

... Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output measured in decibels. Rev Page AD5678 ...

Page 20

... The AD5678 has an on-chip reference with an internal gain of 2. The AD5678-1 has a 1. ppm/°C reference, giving a full- scale output of 2.5 V. The AD5678-2 has a 2 ppm/°C reference, giving a full-scale output The on-board reference is off at power-up, allowing the use of an external reference ...

Page 21

... Figure 24 and Figure 25. The slew rate is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs. SERIAL INTERFACE The AD5678 has a 3-wire serial interface ( SYNC , SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See timing diagram of a typical write sequence ...

Page 22

... Neither an update of the DAC register contents nor a change in the operating mode occurs—see Figure 49 D15 D14 D13 D12 D11 D10 D9 DATA BITS Figure 47. AD5678 Input Register Content for DAC D11 D10 ...

Page 23

... LDAC low the value in the DAC register before powering down ( LDAC high). CLEAR CODE REGISTER The AD5678 has a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive . Bringing the CLR line low clears the contents of the input register and the DAC registers to the data contained in the user-configurable CLR register and sets the analog outputs accordingly ...

Page 24

... AD5678 Table 9. Internal Reference Register Internal REF Register (DB0 Table 10. 32-Bit Input Shift Register Contents for Reference Set-Up Function MSB DB31 to DB28 DB27 DB26 Don’t cares Command bits (C3 to C0) Table 11. Power-Down Modes of Operation DB9 DB8 Operating Mode 0 0 Normal operation ...

Page 25

... Figure 2 . This ground point should be as close as possible to the AD5678. The power supply to the AD5678 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should physically be as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type important that the 0.1 μ ...

Page 26

... ORDERING GUIDE 1 Model Temperature Range AD5678BRUZ-1 −40°C to +105°C AD5678BRUZ-1REEL7 −40°C to +105°C AD5678BRUZ-2 −40°C to +105°C AD5678BRUZ-2REEL7 −40°C to +105°C AD5678ARUZ-2 −40°C to +105°C AD5678ARUZ-2REEL7 −40°C to +105° RoHS Compliant Part. 5.10 5.00 4. 6.40 BSC ...

Page 27

... NOTES Rev Page AD5678 ...

Page 28

... AD5678 NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05299–0–2/11(C) Rev Page ...

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