AD5764 Analog Devices, AD5764 Datasheet - Page 22

• Manufacturer Part Number: AD5764
• Description: Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5764

• Resolution (bits): 16bit
• Dac Update Rate: 1.26MSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5764
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits
to 100. The DAC address bits select with which DAC channel
the data transfer is to take place (see Table 10). The fine gain
register is a 6-bit register and allows the user to adjust the gain
of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB
increments, as shown in Table 16 and Table 17. The adjustment
is made to both the positive full-scale points and the negative
full-scale points simultaneously, each point being adjusted by ½
of one step. The fine gain register coding is twos complement.
Table 16. Programming the Fine Gain Register Bit Map
REG2
1
Table 17. Fine Gain Register Options
Gain Adjustment
+31 LSBs
+30 LSBs
…
+2 LSBs
+1 LSB
No Adjustment (Default)
−1 LSB
−2 LSBs
…
−31 LSBs
−32 LSBs
Table 18. Programming the Offset Register Bit Map
REG2
1
Table 19. AD5764 Offset Register Options
Offset Adjustment
+15.875 LSBs
+15.75 LSBs
…
+0.25 LSBs
+0.125 LSBs
No Adjustment (Default)
−0.125 LSBs
−0.25 LSBs
…
−15.875 LSBs
−16 LSBs
REG1
0
REG1
0
REG0
1
REG0
0
A2
A2
DAC address
A1
FG5
0
0
…
0
0
0
1
1
…
1
1
DAC address
A1
A0
OF7
0
0
…
0
0
0
1
1
…
1
1
A0
DB15:DB8
Don’t care
FG4
1
1
…
0
0
0
1
1
…
0
0
Rev. F | Page 22 of 28
OF6
1
1
…
0
0
0
1
1
…
0
0
DB15:DB6
Don’t care
DB7
OF7
OF5
1
1
…
0
0
0
1
1
…
0
0
FG3
1
1
…
0
0
0
1
1
…
0
0
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to
101. The DAC address bits select with which DAC channel the
data transfer is to take place (see Table 10). The AD5764 offset
register is an 8-bit register and allows the user to adjust the offset
of each channel by −16 LSBs to +15.875 LSBs in increments of
⅛ LSB, as shown in Table 18 and Table 19. The offset register
coding is twos complement.
DB6
OF6
OF4
1
1
…
0
0
0
1
1
…
0
0
DB5
FG5
DB5
OF5
FG2
…
0
1
…
1
1
0
0
1
0
0
OF3
1
1
…
0
0
0
1
1
…
0
0
DB4
FG4
DB4
OF4
DB3
FG3
OF2
…
…
1
1
0
0
0
1
1
0
0
DB3
OF3
FG1
1
1
…
1
0
0
1
1
…
0
0
DB2
FG2
DB2
OF2
OF1
1
1
…
1
0
0
1
1
…
0
0
Data Sheet
DB1
FG1
DB1
OF1
FG0
1
0
…
0
1
0
1
0
…
1
0
OF0
1
0
…
0
1
0
1
0
…
1
0
DB0
FG0
DB0
OF0